Status and perspectives of deep N-well 130 nm CMOS MAPS

Abstract

Deep N-Well (DNW) MAPS were developed in two different flavors to approach the specifications of vertex detectors in dissimilar experimental environments such as the Super B-Factory and the ILC. The first generation of MAPS with on-pixel data sparsification and time stamping capabilities is now available and was tested in a beam for the first time in September 2008. These devices are fabricated in a commercial 130 nm CMOS process, and the triple well structure available in such an ultra-deep submicron technology is exploited by using the deep N-well as the charge-collecting electrode. Because of the high integration density of such a technology, complex digital functions can be included in each pixel, implementing a sparsified readout architecture of the pixel matrix with time stamping. This paper reviews the features of the "ILC class" and "SuperB class" MAPS devices, discussing their different design in terms of pixel pitch, analog signal processing, and digital readout architecture. For SuperB, a data-driven, continuously operating readout scheme was adopted along with a macropixel matrix arrangement, whereas for the ILC the matrix is read out in the long intertrain period. In both versions, the address of hit pixels is transmitted off-chip along with the time stamp. The experimental performance of the chips provides an assessment of the Deep N-Well MAPS potential in view of future applications. The paper also discusses the way forward in the development of these devices, outlining the issues that have to be tackled to design full size Deep N-Well MAPS for actual experiments. These sensors could take advantage from technological advances in microelectronic industry, such as vertical integration. The impact of these new technologies on the design and performance of DNW pixel sensors could be large, with potential benefit for various device features, from the charge collection properties to the digital readout architecture.

Super B Vertex and Vertical integration

“…However, the standard readout architectures of MAPS are based on "rolling shutter" schemes that were devised for much lower hit rates with respect to the Layer0 specifications. Deep N-well (DNW) MAPS [4] have been the first effort in the direction of implementing advanced readout functionalities (as in hybrid pixel detectors) in a monolithic device. In DNW devices, the charge collecting electrode is a deep N-well which is extended over a large fraction of the pixel area.…”

Large area CMOS image sensors

“…However, the integration of PMOS transistors leads to a limitation of imaging performance due to collection of charge by the unrelated N-wells where the PMOS transistors sit [31]. Some groups [32,33] have tried to develop complex pixels by using only NMOS transistors. Although their attempts have partially succeeded, they have to compromise either on the performance of the electronics, for example it is difficult to have a high gain amplifier by using only NMOS transistors in a modern CMOS process, or on the imaging performance, as the unrelated N-wells will start collecting charge as mentioned above.…”

Towards a high performance vertex detector based on 3D integration of deep N-well MAPS

“…The development of deep N-well (DNW) monolithic active pixel sensors (MAPS) was driven by the ambitious goal of implementing advanced readout functionalities (as in hybrid pixel detectors) in a monolithic device. In the first generation of DNW MAPS [1], designed in a 130 nm CMOS technology, data sparsification and time stamping are performed at pixel level, and different readout architectures are implemented taking into account the requirements of vertex detectors at the Super B-Factory [2] and the ILC [3]. In the pixel, the charge collecting electrode (the deep N-well) is extended over a relatively large fraction of the cell area.…”