Stealth-Persist: Architectural Support for Persistent Applications in Hybrid Memory Systems

Alwadi, Mazen; Kommareddy, Vamsee Reddy; Hughes, Clayton; Hammond, Simon David; Awad, Amro

doi:10.1109/hpca51647.2021.00022

Cited by 9 publications

(9 citation statements)

References 45 publications

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“…This framework efectively reduced power consumption by 73.2% and improved delay performance by 20.9%. M. Alwadi et al [6] proposed the Stealth-Persist DRAM/NVM hybrid memory architecture, which could allow applications to use DRAM for performance optimizations while preserving the persistence within the NVM. The Stealth-Persist structure improved the performance of persistent applications by 42.02%.…”

Section: Memory Architecturementioning

confidence: 99%

Experimental Demonstration of STT-MRAM-based Nonvolatile Instantly On/Off System for IoT Applications: Case Studies

Wang

Zhou

et al. 2023

ACM Trans. Embed. Comput. Syst.

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Energy consumption has been a big challenge for electronic devices, particularly, for the battery-powered Internet of Things (IoT) equipment. To address such a challenge, on one hand, low-power electronic design methodologies and novel power management techniques have been proposed, such as nonvolatile memories and instantly on/off systems; on the other hand, the energy harvesting technology by collecting signals from human activity or the environment has attracted widespread attention in the IoT area. However, the system with self-powered energy harvesting may suffer frequent energy failures or fluctuating energy conditions, which degrade system reliability and user experience. Therefore, how to make the system under unreliable power inputs operate correctly and efficiently is one of the most critical issues for the energy harvesting technology. In this paper, we built an instantly on/off system based on nonvolatile STT-MRAM for IoT applications, which can instantly power on/off under different conditions of the harvested energy. The system powers on and operates normally when the harvested energy is enough (over the preset threshold); otherwise, the system powers off and stores the operational data back to the nonvolatile STT-MRAM. We described implementations of the hardware/software co-designed architecture (with image acquisition as an example) based on the commercialized 32MB STT-MRAM, and experimentally demonstrated the system functionality and efficiency under five typical energy harvesting scenarios, including radio-frequency (RF), thermal, solar, piezoelectric and WIFI. Our experimental results show that the power consumption and data restore time were reduced by 15.1 \(\% \) and 714 times respectively in comparison with the DRAM-based counterpart.

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Section: Memory Architecturementioning

confidence: 99%

Experimental Demonstration of STT-MRAM-based Nonvolatile Instantly On/Off System for IoT Applications: Case Studies

Wang

Zhou

et al. 2023

ACM Trans. Embed. Comput. Syst.

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“…Challenge #2: Checkpoint Overheads. By its nature, wholesystem persistence (in line with persistent memory programs [7,8,23,25,34,45,64,71]) should come with performance overheadscompared to volatile execution-and complex hardware changes to control the persist order. For example, with WSP, all store instructions in a region must be reflected inside the non-volatile main memory before proceeding to the next region.…”

Section: Overall Designmentioning

confidence: 99%

“…Given the region formation and register-checkpointing stores delineated by the Capri compiler, the Capri architecture ensures failureatomic execution for each region. Unlike previous studies that assumed failure-atomic software [7,8,25,34,45,64,71], architecture should provide atomic execution in a software transparent manner.…”

Section: Architecture-supported Regionmentioning

confidence: 99%

Capri

Jeong

Zeng

Jung

2022

Proceedings of the 31st International Symposium on High-Performance Parallel and Distributed Computing

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This paper investigates whole-system persistence (WSP) that ensures hassle-free crash consistency for all programs while simultaneously leveraging both advantages of the non-volatile memory technologies: high-density and in-memory persistence. Despite the promising characteristics, there are two challenges that must be addressed to make WSP a reality. First, programs must be able to resume the execution from where they had a failure. Second, failure recovery must be offered to any program including the OS in a transparent manner while minimizing persistence overheads.To this end, this paper presents Capri, a compiler and architecture co-designed scheme for region-level whole-system persistence. First, the Capri compiler partitions program into a series of regions whose boundaries serve as recovery points. Then, the Capri architecture provides the regions with crash consistency through hardware-based atomic updates. Finally, with the novel interplay between the architecture and the compiler, Capri provides failure atomicity on the cheap, i.e., with 0%, 12.4%, and 9.1% performance overheads for SPEC CPU2017, STAMP, and Splash3 benchmarks, respectively. CCS CONCEPTS• Hardware → Emerging architectures; Emerging languages and compilers.

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“…Researchers have considered building pmem with various memory technologies, such as phase-change memory [4,40,41,59,60,69,77], spin-transfer torque RAM (STT-RAM) [1,12,21,25,80,91], resistive RAM [14,75,83,88,90], 3D XPoint [28,31], and DRAM backed by flash [18,49,62,64,87]. Applications can directly load and store data with pmem [3,5,15,28,38,44,45,66,68,76,78,86,87].…”

Section: Persistence Domain and Atomic Durability A Persistence Domainmentioning

confidence: 99%

“…ADR keeps DRAM in self-refresh mode and, more important, places pmem and the write pending queue (WPQ) of memory controller (MC) in the persistence domain [26,27,72], as it guarantees to flush data staying in the WPQ to pmem in case of a power outage. Later Intel extended ADR as eADR that further manages to flush all cache lines to pmem on a crash [2,3,13,24,30]. As a result, eADR frees programmers from manually flushing cache lines to pmem.…”

Section: Introductionmentioning

confidence: 99%

Enabling Atomic Durability for Persistent Memory with Transiently Persistent CPU Cache

Ye¹,

Chen²,

Jiang³

et al. 2022

Preprint

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Persistent memory (pmem) products bring the persistence domain up to the memory level. Intel recently introduced the eADR feature that guarantees to flush data buffered in CPU cache to pmem on a power outage, thereby making the CPU cache a transient persistence domain. Researchers have explored how to enable the atomic durability for applications' in-pmem data. In this paper, we exploit the eADR-supported CPU cache to do so. A modified cache line, until written back to pmem, is a natural redo log copy of the in-pmem data. However, a write-back due to cache replacement or eADR on a crash overwrites the original copy. We accordingly develop Hercules, a hardware logging design for the transaction-level atomic durability, with supportive components installed in CPU cache, memory controller (MC), and pmem. When a transaction commits, Hercules commits on-chip its data staying in cache lines. For cache lines evicted before the commit, Hercules asks the MC to redirect and persist them into inpmem log entries and commits them off-chip upon committing the transaction. Hercules lazily conducts pmem writes only for cache replacements at runtime. On a crash, Hercules saves metadata and data for active transactions into pmem for recovery. Experiments show that, by using CPU cache for both buffering and logging, Hercules yields much higher throughput and incurs significantly fewer pmem writes than state-of-the-art designs.

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Stealth-Persist: Architectural Support for Persistent Applications in Hybrid Memory Systems

Cited by 9 publications

References 45 publications

Experimental Demonstration of STT-MRAM-based Nonvolatile Instantly On/Off System for IoT Applications: Case Studies

Experimental Demonstration of STT-MRAM-based Nonvolatile Instantly On/Off System for IoT Applications: Case Studies

Capri

Enabling Atomic Durability for Persistent Memory with Transiently Persistent CPU Cache

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