Steep switching characteristics of single-gated feedback field-effect transistors

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In this study, we perform simulations to demonstrate neural oscillations in a single silicon nanowire neuron device comprising a gated p–n–p–n diode structure with no external bias lines. The neuron device emulates a biological neuron using interlinked positive and negative feedback loops, enabling neural oscillations with a high firing frequency of ~ 8 MHz and a low energy consumption of ~ 4.5 × 10−15 J. The neuron device provides a high integration density and low energy consumption for neuromorphic hardware. The periodic and aperiodic patterns of the neural oscillations depend on the amplitudes of the analog and digital input signals. Furthermore, the device characteristics, energy band diagram, and leaky integrate-and-fire operation of the neuron device are discussed.

Section: Resultsmentioning

confidence: 99%

Neural oscillation of single silicon nanowire neuron device with no external bias voltage

Woo

Kim

2022

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“…This indicates that the potential barrier heights are varied by the ITCs when the same voltages are applied. A higher potential barrier height implies that the positive feedback loop is eliminated by the gate voltage with a lower absolute value 3 , 4 , 6 . The differences in the potential barrier height based on the ITCs in Fig.…”

Section: Resultsmentioning

confidence: 99%

“…Most FBFET designs have complex fabrication procedures 1 , 2 , or additional gate electrodes 3 , 5 , 6 . Recently, single gate-all-around (GAA) FBFETs with p + - n + - i - n + Si nanowire (SiNW) channels have been proposed to reduce complex device structures and additional gate electrodes 4 . These FBFETs demonstrate high performance because the GAA SiNW structure improves the gate controllability of the potential barrier height in the channel region.…”

Section: Introductionmentioning

confidence: 99%

Simulation studies on electrical characteristics of silicon nanowire feedback field-effect transistors with interface trap charges

Yang

Park

Son

et al. 2021

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In this study, we examine the electrical characteristics of silicon nanowire feedback field-effect transistors (FBFETs) with interface trap charges between the channel and gate oxide. The band diagram, I–V characteristics, memory window, and operation were analyzed using a commercial technology computer-aided design simulation. In an n-channel FBFET, the memory window narrows (widens) from 5.47 to 3.59 V (9.24 V), as the density of the positive (negative) trap charges increases. In contrast, in the p-channel FBFET, the memory window widens (narrows) from 5.38 to 7.38 V (4.18 V), as the density of the positive (negative) trap charges increases. Moreover, we investigate the difference in the output drain current based on the interface trap charges during the memory operation.

“…More recently, simulation studies have demonstrated that the low standby power consumption and reliability of one-transistor SRAM (1T-SRAM) cells, each of which consists of a single-gated feedback field-effect transistor (FBFET), provide a promising possibility for the future of memory devices 17 . Compared with metal–oxide–semiconductor field-effect transistors (MOSFETs) conventionally used in SRAM cells, FBFETs, operating with a positive feedback loop mechanism, exhibit an extremely low subthreshold swing (~ 0 mV/dec), high on/off current ratios, and bi-stable states 18 – 22 . Moreover, the use of 1T-SRAM cells reduces usage area on chips when compared with conventional 6T-SRAM cells constructed with MOSFETs.…”

Section: Introductionmentioning

confidence: 99%

One-transistor static random-access memory cell array comprising single-gated feedback field-effect transistors

Choi

Son

Cho

et al. 2021

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In this study, we fabricated a 2 × 2 one-transistor static random-access memory (1T-SRAM) cell array comprising single-gated feedback field-effect transistors and examined their operation and memory characteristics. The individual 1T-SRAM cell had a retention time of over 900 s, nondestructive reading characteristics of 10,000 s, and an endurance of 108 cycles. The standby power of the individual 1T-SRAM cell was estimated to be 0.7 pW for holding the “0” state and 6 nW for holding the “1” state. For a selected cell in the 2 × 2 1T-SRAM cell array, nondestructive reading of the memory was conducted without any disturbance in the half-selected cells. This immunity to disturbances validated the reliability of the 1T-SRAM cell array.