Several attempts have been made to store charges in the channel regions of silicon transistors, such as in zero-capacitor random-access memories (Z-RAMs), [7,8] metastable DRAMs (MSDRAMs), [9,10] advanced RAMs (A-RAMs), [11,12] and zeroslope and zero-impact ionization RAMs (Z 2-RAMs). [13,14] Among these, Z 2-RAMs are capable of low-voltage operation with high speed, long retention time, and nondestructive reading capability, because of the positive feedback loop. [15] However, electrostatic doping induced by gate bias is required to form a potential well, which is important for the positive feedback loop. [16,17] Although thyristor RAMs (T-RAMs) employ doping regions to form the potential well, external bias is still necessary for TRAMs to retain the stored charges. [18-20] This indispensable bias for holding the stored charges has restricted their use in quasi-nonvolatile memory applications. In this paper, we propose a fully CMOS-compatible p +-n-pn + silicon memory device to enable quasi-nonvolatile memory functionality with high speed, long retention time, and nondestructive reading capability. Using a well-defined potential well in a p +-n-p-n + silicon structure with a gated n-channel region, our device utilizes holes as majority charge carriers for the positive feedback loop, unlike TRAMs which use electrons as majority charge carriers. Hence, our quasi-nonvolatile silicon memory device can retain the charges stored in the channel region without requiring any external bias, for a long time. In addition, the positive-feedback loop enables low-voltage operation, high speed, and nondestructive reading for quasi-nonvolatile memory applications. 2. Results and Discussion A quasi-nonvolatile silicon memory device consists of p +-n-p-n + regions on a silicon-on-insulator (SOI) substrate (Figure 1a). An SiO 2 /poly-Si gate stack is located on the upper side of the n-channel region. The poly-Si gate modulates the potential barrier of the n-channel region; it controls the hole injection from the p + drain region. The p-channel region is designated to block the electron injection from the n + source region. The channel regions also form potential wells; states "1" and "0" are defined by presence and absence of excess charge carriers in the potential wells, respectively. The corresponding energy band diagrams exhibit the difference in the channel region between the two states (Figure 1b). Barrier-height modulation by carrier accumulation in the potential wells is essential for the positive feedback loop, which allows memory operations. Memory hierarchy among conventional memory technologies is one of the main bottlenecks in modern computer systems; alternative memory technologies are thus necessary for quasi-nonvolatile memory applications. Herein, a fully complementary metal-oxide-semiconductor-compatible quasi-nonvolatile memory composed of p +-n-p-n + silicon on a silicon-on-insulator substrate is presented. The quasi-nonvolatile silicon memory device demonstrates highspeed write capability (≤100 ns), long retenti...

In this study, we present the steep switching characteristics of bendable feedback field-effect transistors (FBFETs) consisting of p(+)-i-n(+) Si nanowires (NWs) and dual-top-gate structures. As a result of a positive feedback loop in the intrinsic channel region, our FBFET features the outstanding switching characteristics of an on/off current ratio of approximately 10(6), and point subthreshold swings (SSs) of 18-19 mV/dec in the n-channel operation mode and of 10-23 mV/dec in the p-channel operation mode. Not only can these devices operate in n- or p-channel modes, their switching characteristics can also be modulated by adjusting the gate biases. Moreover, the device maintains its steep SS characteristics, even when the substrate is bent. This study demonstrates the promising potential of bendable NW FBFETs for use as low-power components in integrated circuits or memory devices.

In this study, we propose newly designed feedback field-effect transistors that utilize the positive feedback of charge carriers in single-gated silicon channels to achieve steep switching behaviors. The band diagram, I-V characteristics, subthreshold swing, and on/off current ratio are analyzed using a commercial device simulator. Our proposed feedback field-effect transistors exhibit subthreshold swings of less than 0.1 mV dec, an on/off current ratio of approximately 10, and an on-current of approximately 10 A at room temperature, demonstrating that the switching characteristics are superior to those of other silicon-based devices. In addition, the device parameters that affect the device performance, hysteresis characteristics, and temperature-dependent device characteristics are discussed in detail.

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