Steps Towards Fabricating Cryogenic CMOS Compatible Single Electron Devices

Abstract

We describe the development of a novel silicon quantum bit (qubit) device architecture that involves using materials that are compatible with a Sandia National Laboratories (SNL) 0.35 μm complementary metal oxide semiconductor (CMOS) process intended to operate at 100mK. We describe how the qubit structure can be integrated with CMOS electronics, which is believed to have advantages for critical functions like fast single electron electrometry for readout compared to current approaches using radio frequency techniques. Critical materials properties are reviewed and preliminary characterization of the SNL CMOS devices at 4.2K is presented.Among the many variations of qubits, solid-state approaches are often perceived as appealing because of the existing infrastructure and the demonstration of nano-fabricated devices that are necessary for classical computers. One successful solid-state approach for building a qubit has focused on three dimensional confinement of a single electron spin in a quantum dot.Utilizing electrostatic gates in GaAs heterostrostructures, it has been demonstrated [1] that control of coherent two electron spin states can be achieved in a double quantum dot (DQD). However, one critical challenge to GaAs based structures is the short spin decoherence lifetimes due to the hyperfine interaction with the non-zero nuclear spin of the Ga and As isotopes.Solid-state qubit proposals involving electron spins in silicon are viewed to be more attractive because at cryogenic temperatures they have been shown to have longer decoherence lifetimes (T 2 > 10 ms) [2] due to low spin-orbit interaction and zero total nuclear spin in isotopically enriched 28 Si. Although demonstration of a silicon spin qubit has yet to be achieved, recent progress involving QDs in silicon have shown promising results where single electron electrometry and Pauli-blockaded transport have been demonstrated in ultra thin body silicon-oninsulator substrates [3] and modulation doped Si/SiGe heterostructures [4] [5].Readout within a solid-state qubit formed via double quantum dots is achieved by measuring the charge configuration of the double quantum dot via a capacitively coupled charge sensor (e.g. quantum point contact). The two states of the qubit are the singlet and the (m=0) triplet of the two spin system. Spin information is then inferred by applying a driving voltage to push two electrons into a single quantum dot. There is a significant difference in the exchange energy between the singlet and triplet (singlet is lower) allowing the singlet to form as a double occupied quantum dot but not allowing the triplet to transition to two electron occupation. The singlet state is identified, therefore as the one that has more electron charge in a single quantum dot, sensed capacitvely with the electrometer. High fidelity operation of quantum logic devices requires readout that is faster than the decoherence lifetime of the spin, T 2 . Typically these charge sensors have large inherent impedances (> 26 kΩ) and thus the RC delay is a chal...

Compact modeling of 0.35μm SOI CMOS technology node for 4K DC operation using Verilog-A

“…Current-voltage measurements of p-and n-channel partially-depleted silicon-oninsulator (SOI) MOSFETs that were fabricated in the Sandia National Laboratories 0.35 µm CMOS7 process line [25] were taken at 4 K using a Lakeshore cryogenic probe station. The sample was thermally mounted to a copper chuck inside an evacuated test chamber, and then cooled by continuous-transfer of liquid Helium.…”