STI Effect on Flicker Noise in 0.13-μm RF NMOS

Chan, Calvin M. L.; Jin, Jun-De; Lin, Yu-Syuan; Hsu, Shawn S. H.; Juane, Ying-Zong

doi:10.1109/essder.2006.307648

Cited by 5 publications

(1 citation statement)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Manuscript This letter presents an octagonal dual-gate field-effect transistor (ODGFET) (see Fig. 1) which explores the feasibility of using an extra gate on the shallow trench isolation (STI) to enhance and to adapt the low-frequency noise induced by STI-silicon interfaces [10], [11]. The multigate structure is analogous to that proposed in [12], while the ODGFET is fabricated in the standard CMOS logic technology without additional masks.…”

Section: Introductionmentioning

confidence: 99%

An Octagonal Dual-Gate Transistor With Enhanced and Adaptable Low-Frequency Noise

Chiu

Gong

King

et al. 2011

IEEE Electron Device Lett.

View full text Add to dashboard Cite

As the low-frequency noise of a transistor grows nonnegligible in advanced technologies, the possibility of using noise for computation is becoming an alternative, receiving more and more attention. The ability to control the noise level would further enrich the flexibility of the circuit design. Therefore, this letter presents a dual-gate field-effect transistor in an octagonal shape. By changing the voltage of an extra gate above the shallow trench isolation, the transistor is able to adapt its low-frequency noise over several decades and in a power-efficient manner. The octagonal geometry further makes sufficient a voltage range from 0 to 5 V for the noise adaptation. Moreover, the transistor is fabricated with the standard CMOS logic process without additional masks. All the features underpin the development of large-scale noisy computation in integrated circuits.Index Terms-Dual-gate transistor, low-frequency noise, noise adaptability, shallow trench isolation (STI).

show abstract

Section: Introductionmentioning

confidence: 99%

An Octagonal Dual-Gate Transistor With Enhanced and Adaptable Low-Frequency Noise

Chiu

Gong

King

et al. 2011

IEEE Electron Device Lett.

View full text Add to dashboard Cite

show abstract

D_it Extraction of Nano-node HK/MG nMOSFETs Treated with DPN Process under Diverse Nitrogen Concentration

Huang

Chang

Wang

et al. 2023

2023 IEEE 3rd International Conference on Electronic Communications, Internet of Things and Big Data (ICEIB)

View full text Add to dashboard Cite

Edge-extended Design for Improved Flicker Noise Characteristics in 0.13-μm RF NMOS

Chan

Lin

Huang

et al. 2007

2007 IEEE/MTT-S International Microwave Symposium

View full text Add to dashboard Cite

STI Effect on Flicker Noise in 0.13-μm RF NMOS

Cited by 5 publications

References 8 publications

An Octagonal Dual-Gate Transistor With Enhanced and Adaptable Low-Frequency Noise

An Octagonal Dual-Gate Transistor With Enhanced and Adaptable Low-Frequency Noise

D_it Extraction of Nano-node HK/MG nMOSFETs Treated with DPN Process under Diverse Nitrogen Concentration

Edge-extended Design for Improved Flicker Noise Characteristics in 0.13-μm RF NMOS

Contact Info

Product

Resources

About

STI Effect on Flicker Noise in 0.13-μm RF NMOS

Cited by 5 publications

References 8 publications

An Octagonal Dual-Gate Transistor With Enhanced and Adaptable Low-Frequency Noise

An Octagonal Dual-Gate Transistor With Enhanced and Adaptable Low-Frequency Noise

Dit Extraction of Nano-node HK/MG nMOSFETs Treated with DPN Process under Diverse Nitrogen Concentration

Edge-extended Design for Improved Flicker Noise Characteristics in 0.13-&#x003BC;m RF NMOS

Contact Info

Product

Resources

About

D_it Extraction of Nano-node HK/MG nMOSFETs Treated with DPN Process under Diverse Nitrogen Concentration

Edge-extended Design for Improved Flicker Noise Characteristics in 0.13-μm RF NMOS