Stochastic Decoding of Linear Block Codes With High-Density Parity-Check Matrices

Abstract

Stochastic decoding is a new alternative approach for iterative decoding on graphs. The capability of stochastic decoding has been recently validated for decoding Low-Density Parity-Check (LDPC) codes. This article extends the application of the stochastic approach to decode linear block codes with highdensity Parity-Check Matrices (PCMs) such as Bose-Chaudhuri-Hocquenghem (BCH) codes, Reed-Solomon (RS) codes and, block turbo codes based on BCH component codes. We show how the stochastic approach, despise its bit-serial nature, is able to generate soft-output information for iterative Soft-Input Soft-Output (SISO) decoding. This article describes the structure of high-degree stochastic variable nodes used in codes with high-density PCMs. Simulation results for a (128, 120) BCH code, a (31, 25) and a (63, 55) RS code and, a (256, 121) and a (1024, 676) BCH block turbo code demonstrate decoding performance close to the iterative SISO decoding with floatingpoint implementation.

Stochastic Decoding of Turbo Codes

“…Stochastic computations have been recently considered to decode FEC codes. Early stochastic decoding has been applied to some short error correcting codes such as the (7,4) Hamming code [4] and a (256,121) block turbo code based on two (16,11) Hamming codes [7]. The first implementation of a stochastic decoder with a (16,8) LDPC code was described in [8].…”

“…An improved stochastic decoding approach was then proposed to decode practical LDPC codes [9], [10]. This approach was also extended to well-known linear block codes with high-density parity-check matrices, namely BCH codes, Reed Solomon codes and product codes [11]. When compared with conventional Sum-Product implementations, stochastic decoding could provide near-optimal performance for practical LDPC codes.…”

Design and FPGA implementation of stochastic turbo decoder

“…High data rates and architecture efficiencies were achieved thanks to many recent improvements [7] [8]. In addition, this approach was extended to well-known linear block codes with high-density parity-check matrices, namely BCH codes, Reed Solomon codes and product codes [9]. Moreover, stochastic decoding is also of high interest for low power decoders [10] and fault-tolerant nanoscale circuits [11].…”

Tracking Forecast Memories for Stochastic Decoding

“…The stochastic LDPC decoder in [21] is able to provide a maximum throughput of 1.66 Gb/s. The EM-based stochastic decoding method was also extended to the important classes of Bose Chaudhuri Hocquenghem (BCH) codes, Reed-Solomon (RS) codes and Turbo product codes in [20] and also for decoding non-binary LDPC codes in [18].…”