Stochastic Flash Analog-to-Digital Conversion

Weaver, Skyler; Hershberg, Benjamin; Kurahashi, P.; Knierim, Dan; Moon, Un-Ku

doi:10.1109/tcsi.2010.2050225

Cited by 82 publications

(51 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The SF-ADC uses comparators' input offsets as reference levels and so does not require any offset cancellation or calibration. The comparator is designed with minimum sized transistors in [8] and any offset cancellation is not used. This leads to decreasing the area occupation.…”

Section: Sf-adc and Its Linearization Techniquementioning

confidence: 99%

“…This approach has led to the proposal of stochastic flash ADCs (SFADCs), which apply the statistical nature of comparator offsets to detect signals below the offset level thereby maintain good dynamic range even in fine-process devices with substantial mismatch [8,9,10]. This technique originates from a detection principle of small signal with noise, so-called stochastic resonance [11,12,13,14].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

An offset distribution modification technique of stochastic flash ADC

Asano

Hirai

Tani

et al. 2016

IEICE Electron. Express

View full text Add to dashboard Cite

A new non-linearity reduction technique for stochastic flash ADC (SF-ADC) is proposed, focusing on distribution of comparator inputreferred offsets. The SF-ADC test chip fabricated in a 130-nm CMOS process demonstrated the proposed technique can improve SNDR. In addition, the digital re-quantization also can improve the linearity more, where quantization level and fractional correction can be optimized using genetic algorithm.

show abstract

Section: Sf-adc and Its Linearization Techniquementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An offset distribution modification technique of stochastic flash ADC

Asano

Hirai

Tani

et al. 2016

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…Recently, a new ADC, referred to as the stochastic ADC, has been reported [5]. It uses device mismatch based on similar architectures.…”

Section: Introductionmentioning

confidence: 99%

Design of a 500-MS/s stochastic signal detection circuit using a non-linearity reduction technique in a 65-nm CMOS process

Ham

Matsuoka

Wang

et al. 2011

IEICE Electron. Express

View full text Add to dashboard Cite

Abstract:A stochastic signal detection circuit that uses a nonlinearity reduction technique is designed using a 65-nm CMOS process. The fabricated chip demonstrates the feasibility of stochastic signal detection at 500 MS/s. Keywords: signal detection, comparator, mismatch, CMOS Classification: Integrated circuits I, vol. 57, no. 11, pp. 2825I, vol. 57, no. 11, pp. -2833I, vol. 57, no. 11, pp. , Nov. 2010 J. Lin and B. Haroun, "An embedded 0.8 V/480 μW 6b/2 MHz flash ADC in 0.13-μm digital CMOS process using a nonlinear double interpolation technique," IEEE J. References

show abstract

“…In circuit system research, [3] presents a design that explores the idea of high resolution quantization. Assuming uniform input over [−σ, σ], their design corresponds to n in the range of 1000 to 2000, and τ (x) = δ (x − 1.078σ) /2 + δ (x + 1.078σ) /2, with the rationale of making the resulting density λ = τ * φ as uniform as possible in the signal range [−σ, σ].…”

Section: B Comparison With Stochastic Adcmentioning

confidence: 99%

“…This problem is motivated by Analogto-Digital Converter (ADC) design with imperfect comparators, where the comparator reference voltages are subject to stochastic manufacture variations, which becomes increasing salient as modern CMOS design approaches the physical limits of scaling. A series of work in circuit systems [1]- [3] have employed redundancy and/or reconfigurability to tackle this issue, in the context of Flash ADC design. On the other hand, While there exists some theoretical investigation of imperfect scalar quantizer and ADC (e.g., see [4] and the references therein), they treat the ADC design as given and aim to improve the quantization (estimation) performance via post processing.…”

Section: Introductionmentioning

confidence: 99%

Scalar quantization with noisy partitions and its application to Flash ADC design

Wang¹,

Polyanskiy²,

Wornell³

2014

2014 IEEE International Symposium on Information Theory

View full text Add to dashboard Cite

Abstract-Motivated by recent circuit designs for Flash ADCs with imperfect comparators, we investigate the problem of scalar quantization with noisy partition points, where the partition point locations are perturbed from the designated values by noise during the placement process. For this problem setting, we derive a high resolution approximation for mean square error, and analyze the optimal partition point density accordingly. Our results indicate that it is necessary to take the effect of noise into account in the design process. In particular, we derive the optimal partition point density when the input distribution is Gaussian or uniform, and show when noise variance exceeds a certain threshold, a peculiar phase transition occurs and the optimal point density degenerates into a delta function at the origin. These theoretical results allow to optimize the design of flash ADCs and gain 1 bit in resolution over existing designs.

show abstract

Stochastic Flash Analog-to-Digital Conversion

Cited by 82 publications

References 9 publications

An offset distribution modification technique of stochastic flash ADC

An offset distribution modification technique of stochastic flash ADC

Design of a 500-MS/s stochastic signal detection circuit using a non-linearity reduction technique in a 65-nm CMOS process

Scalar quantization with noisy partitions and its application to Flash ADC design

Contact Info

Product

Resources

About