Storage Estimation and Design Space Exploration Methodologies for the Memory Management of Signal Processing Applications

Abstract

The storage requirements in data-dominated signal processing systems, whose behavior is described by array-based, loop-organized algorithmic specifications, have an important impact on the overall energy consumption, data access latency, and chip area. This paper gives a tutorial overview on the existing techniques for the evaluation of the data memory size, This research was sponsored in part by the U.S. National Science Foundation (DAP 0133318). F. Balasa (B)Southern Utah University, Cedar City, UT, USA e-mail: balasa@suu.edu which is an important step during the early stage of system-level exploration. The paper focuses on the most advanced developments in the field, presenting in more detail (1) an estimation approach for nonprocedural specifications, where the reordering of the loop execution within loop nests can yield significant memory savings, and (2) an exact computation approach for procedural specifications, with relevant memory management applications -like, measuring the impact of loop transformations on the data storage, or analyzing the performance of different signal-tomemory mapping models. Moreover, the paper discusses typical memory management trade-offs -like, for instance, between storage requirement and number of memory accesses -taken into account during the exploration of the design space by loop transformations in the system specification.

Array Size Computation under Uniform Overlapping and Irregular Accesses

“…For instance, for the Darwin algorithm with 27 arrays we observe the longest time for the overall flow, i.e. 2.5s [Balasa et al 2008]. Assuming that the array size computation for polyhedral approach takes 81 ms, which was the lower value obtained during our experimentations, then the total time dedicated to the computation of the maximum alive elements for all the arrays is 2.187s, which is the dominant task as it takes 88% of the total time.…”

“…The time required to explore one instance becomes now an important factor in the overall time of DSE, as we need to apply this step a lot of times in order to explore a set of different scenarios for the application under study and we have to apply this process for all the arrays existing in the application. To provide an intuition over the gains in the overall flow, we will use the information provided in [Balasa et al 2008] using the STOREQ, a tool developed for main parts of the steps [Kjeldsberg et al 2003]. This tool is typically used in the inner core of a loop transformation exploration kernel.…”

Loop scheduling with memory access reduction subject to register constraints for DSP applications

“…Various approaches have been investigated to reduce memory accesses . Two compile‐time optimizations, redundant load/store elimination and loop‐invariant load/store migration, can reduce explicit redundant memory accesses .…”

Memory bounds for the distributed execution of a hierarchical Synchronous Data-Flow graph

“…As explained in [21], the former optimization techniques often require a partial system synthesis and the execution of time-consuming algorithms. Although these techniques provide an exact or highly optimized memory requirement, they may be too slow to be used in the rapid prototyping context.…”

“…Although these techniques provide an exact or highly optimized memory requirement, they may be too slow to be used in the rapid prototyping context. In [21], Balasa et al survey existing estimation techniques that provide a reliable memory size approximation in a reasonable computation time. The main difference between these estimation techniques and our bounding method is the abstraction level considered.…”