Strain and wafer curvature of 3C‐SiC films on silicon: influence of the growth conditions

Zieliński, Marcin; Ndiaye, S.; Chassagne, Thierry; Juillaguet, Sandrine; Lewandowska, R.; Portail, Marc; Leycuras, A.; Camassel, Jean

doi:10.1002/pssa.200674130

Cited by 61 publications

(49 citation statements)

References 13 publications

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“…More significantly, 3C-SiC can be deposited on singlecrystal Si, which reduces the cost and enables large area growth [2][3][4]. However, the poor crystalline quality of the epitaxial layers and large film stress (wafer warpage), which result from the large lattice mismatch ($20%) and difference of thermal expansion coefficient ($8%) between the Si substrate and 3C-SiC film, have limited the development of 3C-SiC/Si [5,6]. Since Nishino et al achieved single-crystal growth up to 4 mm thickness on Si substrate by using a carbonized buffer-layer approach in 1980, further extension and improvement have been conducted to fabricate largerarea and higher-quality single-crystal SiC layers [7][8][9].…”

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confidence: 98%

“…On the other hand, several efforts have been made to control the wafer [11], Si/Ge [12], and a ''checker-board'' carbonization Si wafer [13]. Despite these attempts, large warpage remains in the 3C-SiC/Si system and 3C-SiC wafers after removing Si from 3C-SiC/Si, especially with the increase of SiC thickness and area, which could lead to difficulties in applying these materials in basic processing tools such as photolithography [3,6,14]. Wafer warpage is determined by the residual stress in the hetero-structure system.…”

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confidence: 99%

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Saddle‐shape warpage of thick 3C‐SiC wafer: Effect of nonuniform intrinsic stress and stacking faults

Sun

Izumi

Sakai

et al. 2011

Physica Status Solidi (b)

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The technique of thick cubic silicon carbide (3C-SiC) film (up to 300 mm) deposition on undulant-Si substrates is very effective in reducing stacking faults and other planar defects of 3C-SiC wafers. However, after removing the Si substrate, 3C-SiC wafers show anisotropic warpage involving large convex curvature in the direction perpendicular to the ridge of undulation and slight concave curvature in the parallel direction, i.e., saddle shape. In this paper, we have discussed the origin of the warpage of 3C-SiC wafers. From ex situ curvature measurements and stress calculation, we found that large compressive intrinsic stress was generated during hightemperature growth (1623 K) in both parallel and perpendicular directions. To investigate the intrinsic stress distribution along the 3C-SiC film thickness direction, we performed reactive ion etching (RIE) on 3C-SiC film and determined the dependence of the SiC/Si system curvature on the remaining 3C-SiC thickness. The intrinsic stress component perpendicular to the ridge of undulation showed nonuniform distribution along the film thickness. Below the 50 mm thickness region, the distribution presented large variation. The obtained intrinsic stress distribution was very similar to the stacking fault distribution, which showed high density near the SiC/Si interface and rapidly decreased within 50 mm apart from the interface. The simulation by finite element method (FEM) has clearly explained that the anisotropic warpage of SiC wafer was led by the intrinsic stress distribution in a quantitative manner. Microstructure changes induced by the stacking fault reduction process (stacking fault collision) would be the cause of the intrinsic stress variation.

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confidence: 98%

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confidence: 99%

Saddle‐shape warpage of thick 3C‐SiC wafer: Effect of nonuniform intrinsic stress and stacking faults

Sun

Izumi

Sakai

et al. 2011

Physica Status Solidi (b)

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“…This process was used for the three 3C-SiC films grown on (100) Si substrates 9 at 2.45, 3.21, 4 lm/h of growth rate measured at the wafer center. The FTIR measurements show that, due to the lack of wafer rotation during film growth, the sample thickness varied between 2.3 lm (center) and 2.5 lm (edge) across the 50-mm wafer diameter in a direction [110], parallel to the main flat (transverse to the flow direction), while the thickness varied between 3.3 lm (upstream) and 2.2 lm (downstream) along a direction [1][2][3][4][5][6][7][8][9][10] perpendicular to the main flat (flow direction).…”

Section: Methodsmentioning

confidence: 99%

“…It was observed that reducing the growth rate (and thus increasing the growth duration) resulted in an inversion of the stress from tensile to compressive. 5 For a better understanding of the impact that the growth rate has on the residual stress and film crystallinity of low pressure chemical vapor deposition (LPCVD)-grown 3C-SiC heteroepitaxial films, in this work, three 3C-SiC films of the same thickness were grown at three different deposition rates on individual 50-mm diameter (100) Si wafers. In this work, through profilometer analysis, microRaman, x-ray diffraction (XRD), and micromachined freestanding structures, crystal quality, and residual stress related to the growth rate were evaluated.…”

Section: Introductionmentioning

confidence: 99%

Stress nature investigation on heteroepitaxial 3C–SiC film on (100) Si substrates

et al. 2012

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To understand the impact that the growth rate has on the residual stress of chemical vapor deposition-grown 3C-SiC heteroepitaxial films on Si substrates, growth experiments were performed. The film thickness was held constant at ;2.5 lm independent of the growth rate so as to allow for direct film comparison as a function of the growth rate. Stress analysis performed by profilometer curvature measurement, livqo-Raman shift analysis and micro-machined freestanding structures, show an apparent disagreement about the stress nature. This incongruity between the experimental data can be explained assuming a strong stress field located in the substrate related to defects generated in the silicon during the growth process.

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“…During the growth of 3C-SiC on silicon, lattice mismatch caused by the difference in lattice constant and thermal misfit due to the differences in thermal expansion coefficient will contribute to large residual stress (Nagasawa and Yagi., 1997, Sun, et al, 2012, Veprek, et al, 2009, Zielinski, et al, 2007, Severino, et al, 2007. This stress can induce a high dislocation density and wafer warpage in device manufacture.…”

Section: Introductionmentioning

confidence: 99%

Reaction pathway analysis for differences in motion between C-core and Si-core partial dislocation in 3C-SiC

Yang

Izumi

Muranaka

et al. 2015

Mechanical Engineering Journal

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Reaction pathway analysis was carried out to investigate the activation energy barriers of Shockley partial dislocation mobility in 3C-SiC. For each partial dislocation, there are two types of dislocations according to which kind of atom, Si or C, comprises the core edge of the dislocation line. In this paper, the partial dislocation is simulated by Vashishta potential functions. Moreover, the activation energy of kink pair nucleation and kink migration are investigated by reaction pathway analysis. The dependence of the activation energy on the driving shear stress is also discussed. The results show that during kink migration, 30° partial dislocations have a lower activation energy barrier than 90° partial dislocation. And, C-core partial dislocations have a higher activation energy barrier than Si-core dislocations for both degrees of partial dislocations during kink migration and nucleation. This conclusion is consistent with the experimental result that Si-core dislocations migrate more readily than C-core dislocations. Furthermore, we found that partial dislocations with larger distance between the dangling bond atoms along the dislocation line have higher activation energy barriers. Based our calculation results, we propose new models to account for the morphological differences in the dislocation lines.

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Strain and wafer curvature of 3C‐SiC films on silicon: influence of the growth conditions

Cited by 61 publications

References 13 publications

Saddle‐shape warpage of thick 3C‐SiC wafer: Effect of nonuniform intrinsic stress and stacking faults

Saddle‐shape warpage of thick 3C‐SiC wafer: Effect of nonuniform intrinsic stress and stacking faults

Stress nature investigation on heteroepitaxial 3C–SiC film on (100) Si substrates

Reaction pathway analysis for differences in motion between C-core and Si-core partial dislocation in 3C-SiC

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