Strain Enhanced nMOS Using <i>In Situ</i> Doped Embedded $\hbox{Si}_{1 - x}\hbox{C}_{x}$ S/D Stressors With up to 1.5% Substitutional Carbon Content Grown Using a Novel Deposition Process

Dark-field holography, a new transmission electron microscopy technique for mapping strain distributions at the nanoscale, is used to characterize strained-silicon n-type transistors with a channel width of 65 nm. The strain in the channel region, which enhances electron mobilities, is engineered by recessed Si0.99C0.01 source and drain stressors. The strain distribution is measured across an array of five transistors over a total area of 1.6 μm wide. The longitudinal tensile strain reaches a maximum of 0.58%±0.02% under the gate oxide. Theoretical strain maps obtained by finite element method agree well with the experimental results.

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“…22 TEM samples were prepared by focus ion beam for ͓110͔ zone axis observations ͓Fig. 1͑a͔͒ to a thickness of about 150 nm.…”

mentioning

confidence: 99%

Strain mapping of tensiley strained silicon transistors with embedded Si1−yCy source and drain by dark-field holography

Hüe

Hÿtch

Houdellier

et al. 2009

Applied Physics Letters

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“…Cyclic deposition and etching (CDE) was applied to achieve SEG. [11][12][13][14][15][16] Unlike the co-flow process, by which precursors and HCl and/or Cl 2 etchant were simultaneously supplied into the chamber, 17 separated deposition and etching steps made up 1 cycle of the CDE process. During the deposition step, SiGe was simultaneously nucleated on Si and nitrides.…”

Section: Methodsmentioning

confidence: 99%

Selective epitaxial growth of stepwise SiGe:B at the recessed sources and drains: A growth kinetics and strain distribution study

et al. 2016

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The selective epitaxial growth of Si1-xGex and the related strain properties were studied. Epitaxial Si1-xGex films were deposited on (100) and (110) orientation wafers and on patterned Si wafers with recessed source and drain structures via ultrahigh vacuum chemical vapor deposition using different growing steps and Ge concentrations. The stepwise process was split into more than 6 growing steps that ranged in thicknesses from a few to 120 nm in order to cover the wide stages of epitaxial growth. The growth rates of SiGe on the plane and patterned wafers were examined and a dependence on the surface orientation was identified. As the germanium concentration increased, defects were generated with thinner Si1-xGex growth. The defect generation was the result of the strain evolution which was examined for channel regions with a Si1-xGex source/drain (S/D) structure.

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“…[43] Laser annealing using fast recrystallization at locally high temperatures is reported to provide relatively low substrate capacitance and low sheet resistance, R s . [44] It was reported that SPE annealing with an additional millisecond FLA anneal provides the highest carbon substitution. [45] Clustered carbon implantation has been proposed as an alternative source of carbon that can achieve higher throughput due to removal of the requirement of pre-amorphization implantation.…”

Section: Sic Nmos S/d Epimentioning

confidence: 99%

Review paper: Advanced source and drain technologies for low power CMOS at 22/20 nm node and below

Song

Blatchford

2011

Electron. Mater. Lett.

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TX 75243, U.S.A As device dimensions scale, optimization of the source and drain portions of MOSFETs becomes more important in order to reduce parasitic resistance and capacitance, and thus ultimately improve overall device performance. Reduction of parasitic resistance requires careful optimization of dopant incorporation and activation. In current cutting-edge technologies, the source/drain region also plays a key role in improving channel carrier mobility though process-induced strain. Introducing various alloys into NiSi and/or implanting appropriate elements has shown to give significant reduction of the Schottky barrier height between NiSi and Si, thereby improving resistance. In this paper, we review key aforementioned source and drain engineering technologies relevant to the 22/20 nm logic technology node and below.

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Strain Enhanced nMOS Using In Situ Doped Embedded $\hbox{Si}_{1 - x}\hbox{C}_{x}$ S/D Stressors With up to 1.5% Substitutional Carbon Content Grown Using a Novel Deposition Process

Cited by 35 publications

References 7 publications

Strain mapping of tensiley strained silicon transistors with embedded Si1−yCy source and drain by dark-field holography

Strain mapping of tensiley strained silicon transistors with embedded Si1−yCy source and drain by dark-field holography

Selective epitaxial growth of stepwise SiGe:B at the recessed sources and drains: A growth kinetics and strain distribution study

Review paper: Advanced source and drain technologies for low power CMOS at 22/20 nm node and below

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