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We report a CMOS-compatible embedded siliconcarbon (eSiC) source/drain stressor technology with NMOS performance enhancement. The integration includes up to 2.6% substitutional carbon (Csub) epitaxial Si:C and laser spike annealing (LSA) for increased Csub incorporation. 26% channel resistance (Rch) reduction and ll% Idlin-loff enhancement for 0.5% Csub and 60% Rch reduction for 2.2% Csub are demonstrated.

Si1-yCy films grown lattice matched into recessed source drain areas can produce a tensile strained Silicon channel, which in turn will enhance electron mobility. We demonstrate a Cyclical Deposition Etch (CDE) process that consists of a nonselective deposition, (epitaxial growth over the exposed crystalline Silicon areas of the source and drain and amorphous (a) or polycrystalline deposition over the dielectric areas) together with a subsequent selective removal of a-material from the insulator, with negligible removal of epitaxial material from source and drain areas. To make such an approach production worthy, two requirements are essential: 1) a high growth rate (GR) with a low a/epi GR ratio, and 2) a high etch rate (ER) with a high a/epi ER ratio. We focus on the integration and defect formation aspect of our CDE process on patterned substrates.

In this paper we calculate throughput based on recipe overhead (chamber etch, wafer load, wafer bake, cool down, unload) and deposition time for "true" SEG or the core cycle time (deposition, purge, etch, purge times) for a CDE process. In the latter case an average, effective growth rate (GR) can be extracted by dividing the deposited thickness per cycle by the cycle time. In high volume manufacturing (HVM) high SEG GR are necessary for high throughput and low Cost of Ownership (CoO). High GR also enable high substitutional carbon levels [C]sub in dilute Si:C alloys. In this work all experiments were exclusively performed using Silcore® (ASM trademarked version of Si3H8). Due to the high GR at low process temperature, high [C]sub and low films resistivities can be obtained independent of the two different Cl containing etch chemistries that were used in this study. The main challenge of using Cl2 compared to the ASM proprietary etch chemistry is the 25-30 times lower etch rate selectivity (~7 vs. ~190) of a-SiCP over epi-SiCP. As a result of the low etch rate selectivity using a Cl2 etch chemistry, a significant portion of the epitaxial SiC:P is also etched with the a-SiCP. This results in a low effective growth rate which has a deleterious impact to throughput.

Embedded Si1-y-zCyPz films selectively grown into recessed source drain areas of NFET devices has been shown to produce a tensile strained Silicon channel, which in turn enhances electron mobility and transistor performance [1]. In order to obtain and maintain high substitutional carbon levels during deposition/processing low growth temperatures and high growth rates (GR) have to be employed. Carbon substitutionality was demonstrated to be almost complete for Si0.97C0.02P0.01. Excellent crystalline quality was demonstrated on bare wafers by XRD. The absence of crystalline defects and perfect selectivity were confirmed by TEM and SEM on patterned 200 and 300 mm wafers.