Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

Witters, L.; Arimura, Hiroaki; Sebaai, Farid; Hikavyy, Andriy; Milenin, Alexey; Loo, Roger; Keersgieter, A. De; Eneman, G.; Schram, T.; Wostyn, Kurt; Devriendt, K.; Schulze, Andreas; Lieten, Ruben; Bilodeau, S.; Cooper, Emanuel I.; Storck, P.; Chiu, E.; Vrancken, C.; Favia, P.; Vancoille, E.; Mitard, J.; Langer, Róbert; Opdebeeck, A.; Holsteyns, Frank; Waldron, Niamh; Barla, K.; Heyn, V. De; Mocuta, D.; Collaert, N.

doi:10.1109/ted.2017.2756671

Cited by 46 publications

(33 citation statements)

References 20 publications

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“…The RMG process still will work well for the 7 nm and 5 nm technology node with SiGe nanowires through selectively removing the Si sacrificial layer from the SiGe channel material [ 234 ]. Meanwhile, for technology nodes 3 nm and beyond, the sacrificial material is SiGe and will be selectively removed from Ge channel [ 235 , 236 , 237 ].…”

Section: Wet Cleaningmentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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Section: Wet Cleaningmentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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“…The sacrificial material is SiGe and will be selectively removed from the Ge channel [131,132,133]. For example, SiGe can be selectively etched to Ge in diluted TMAH 5–25% at 90 °C.…”

Section: Etching Evolutionmentioning

confidence: 99%

Miniaturization of CMOS

Radamson

Zhang

et al. 2019

Micromachines

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When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

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“…V GS ≤ V TH . After providing V GS ≥ V TH , surface potential starts increasing resulting in increase in injection electron exponentially (movement of electron is from source to body in case of N-type channel and movement of electron from body to source in case of P-type channel) is seen because of increase in energy level of electrons [16][17][18][19][20][21][22].…”

Section: Restrictions Imposed By Electron Drift Characteristicsmentioning

confidence: 99%

Double Gate MOSFETs: Assessment with Single Gate MOSFETs with Channel Material Configuration, its Structure Orientation and Future Applications

Singh*,

Kumar

2020

IJITEE

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In last 3 decades or so as we have scale down the MOSFETs with single-gate to nanometer region in order to maintain the performance level high but single gate MOSFETs still continue to suffers from the interface coupling, channel orientation, channel mobility, leakage current, switching delay and latch up. Further, the additional parameters such as short channel effects (DIBL, GIDL), body effect, hot electron effect, punch through effect, surface scattering, impact ionization, subthreshold swing and volume inversion has shown result inform of increase in leakage current, decrease of inversion charge and decrease in the drive current since double-gate MOSFET came into existence, which relies on the exploration of novel higher mobility channel materials which might perform even better than current existing single gate MOSFETs. This paper compares double-gate MOSFET configuration and single-gate MOSFET configuration using different performance parameters and channel material configuration and additionally assessed different channel materials along with its structure orientation and the future applications.

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Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

Cited by 46 publications

References 20 publications

State of the Art and Future Perspectives in Advanced CMOS Technology

State of the Art and Future Perspectives in Advanced CMOS Technology

Miniaturization of CMOS

Double Gate MOSFETs: Assessment with Single Gate MOSFETs with Channel Material Configuration, its Structure Orientation and Future Applications

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