Strained Si CMOS (SS CMOS) technology: opportunities and challenges

Rim, K.; Anderson, Ron; Boyd, D.; Cardone, F.; Chan, K.; Chen, H.; Christansen, S.; Chu, J. O.; Jenkins, K.A.; Kanarsky, T.; Koester, Steven J.; Lee, B.H.; Lee, K.; Mazzeo, V.; Mocuta, A.; Mocuta, D.; Mooney, P. M.; Oldiges, P.; Ott, J. A.; Ronsheim, P.; Roy, R.; Steegen, An; Yang, Min; Zhu, Huilong; Ieong, M.; Wong, H.-S. Philip

doi:10.1016/s0038-1101(03)00041-8

Cited by 93 publications

(52 citation statements)

References 16 publications

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“…Concerning the result of Rim et al, the lack of experimental details does not allow us to explain this mobility enhancement [7]. For the other data plotted on this figure, the technological processes for NMOS fabrication including a GBL were similar and lead to close mobility values [11,45,47]. Our results obtained from Monte Carlo simulation are in accordance with the best experimental mobility enhancements [7,12,13].…”

Section: Effect Of Strain On Electron Mobilitysupporting

confidence: 76%

“…6 the electron mobility enhancement relative to bulk Si as a function of x for our results (open symbols) and for experimental data (full symbols). The saturation of the mobility when x reaches 0.15 is also evidenced experimentally (see data from Refs [11,47]), and increasing the Ge content above 0.20 has no more effect on mobility [11]. Nevertheless, the plot of Fig.…”

Section: Effect Of Strain On Electron Mobilitysupporting

confidence: 62%

“…The experimental electron mobilities versus E eff are generally extracted from the linear regime of drain current I D (V DS ) for long surface-channel strained Si n-MOSFETs. Experimentally, the mobility enhancement is nearly constant over the full range of effective field, whatever x [11,47]: see for example the results of Currie et al in the insert of Fig. 4 [11].…”

Section: Effect Of Strain On Electron Mobilitymentioning

confidence: 95%

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Electron effective mobility in strained-Si/Si1−xGex MOS devices using Monte Carlo simulation

Aubry-Fortuna

Dollfus

Galdin‐Retailleau

2005

Solid-State Electronics

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Based on Monte Carlo simulation, we report the study of the inversion layer mobility in n-channel strained Si/ Si 1-x Ge x MOS structures. The influence of the strain in the Si layer and of the doping level is studied. Universal mobility curves µ eff as a function of the effective vertical field E eff are obtained for various state of strain, as well as a fall-off of the mobility in weak inversion regime, which reproduces correctly the experimental trends. We also observe a mobility enhancement up to 120 % for strained Si/ Si 0.70 Ge 0.30 , in accordance with best experimental data. The effect of the strained Si channel thickness is also investigated: when decreasing the thickness, a mobility degradation is observed under low effective field only.

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Section: Effect Of Strain On Electron Mobilitysupporting

confidence: 76%

Section: Effect Of Strain On Electron Mobilitysupporting

confidence: 62%

Section: Effect Of Strain On Electron Mobilitymentioning

confidence: 95%

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Electron effective mobility in strained-Si/Si1−xGex MOS devices using Monte Carlo simulation

Aubry-Fortuna

Dollfus

Galdin‐Retailleau

2005

Solid-State Electronics

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“…[1][2][3] More recently, there has been renewed interest in using Ge as a channel material due to its higher hole (1900 vs. 500 cm 2 /V s) and electron (3900 vs. 1400 cm 2 /V s) mobility compared to Si. [4][5][6][7] Crystalline oxides are also being considered by the semiconductor industry as next-generation high-k dielectrics.…”

Section: Introductionmentioning

confidence: 99%

Atomic layer deposition of crystalline SrHfO3 directly on Ge (001) for high-k dielectric applications

McDaniel

et al. 2015

Journal of Applied Physics

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The current work explores the crystalline perovskite oxide, strontium hafnate, as a potential high-k gate dielectric for Ge-based transistors. SrHfO3 (SHO) is grown directly on Ge by atomic layer deposition and becomes crystalline with epitaxial registry after post-deposition vacuum annealing at ∼700 °C for 5 min. The 2 × 1 reconstructed, clean Ge (001) surface is a necessary template to achieve crystalline films upon annealing. The SHO films exhibit excellent crystallinity, as shown by x-ray diffraction and transmission electron microscopy. The SHO films have favorable electronic properties for consideration as a high-k gate dielectric on Ge, with satisfactory band offsets (>2 eV), low leakage current (<10−5 A/cm2 at an applied field of 1 MV/cm) at an equivalent oxide thickness of 1 nm, and a reasonable dielectric constant (k ∼ 18). The interface trap density (Dit) is estimated to be as low as ∼2 × 1012 cm−2 eV−1 under the current growth and anneal conditions. Some interfacial reaction is observed between SHO and Ge at temperatures above ∼650 °C, which may contribute to increased Dit value. This study confirms the potential for crystalline oxides grown directly on Ge by atomic layer deposition for advanced electronic applications.

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“…Over the past several decades, there has been an interest in strained-Si/SiGe/Si-substrate heterostructures because a change in band structure and density of states due to strain produces an enhancement in the mobility of charge carriers [1][2][3]. In an n-MOSFET device with channel regions formed by pseudomorphic growth of strained Si on a relaxed Si 0.7 Ge 0.3 template, the effective electron mobility reached a 1010 cm 2 V −1 s −1 value [4], which is 80% higher than that of normal silicon (560 cm 2 V −1 s−1).…”

Section: Introductionmentioning

confidence: 99%

Structural characterization of strained silicon grown on a SiGe buffer layer

Jang

Phen

Gerger

et al. 2008

Semicond. Sci. Technol.

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The microstructure of about 50 nm thick strained-Si/Si 0.7 Ge 0.3 /graded-SiGe/Si-substrate layers grown by MBE (molecular beam epitaxy) was characterized using high-resolution x-ray based characterization techniques. The degree of relaxation of the Si-capping layer after a thermal anneal at 800• C for 30 min was determined using reciprocal space map (RSM) scans recorded around the (1 1 3) diffraction plane. However, since a RSM is not suitable when the strain relaxation is very small, x-ray reflectivity (XRR) and omega rocking curves (ω-RCs) were employed for the relaxation study. XRR spectra were collected and analyzed to obtain thickness, Ge concentration and surface/interfacial roughness information of the as-grown and annealed samples. ω-RCs were performed in order to investigate the crystalline quality of the samples. It was found that the annealed strained layer showed higher Lorentzian fraction in ω-RCs and misfit defect density which were caused by strain relaxation. In addition, the results showed that after the annealing process the broadening in the tail region of the ω-RCs was indicative of a change in the coherence length distribution of the crystallite size. The misfit defects and surface morphology obtained from transmission electron microscopy (TEM) and atomic force microscopy (AFM) investigations were consistent with results obtained from the x-ray based characterization techniques.

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Strained Si CMOS (SS CMOS) technology: opportunities and challenges

Cited by 93 publications

References 16 publications

Electron effective mobility in strained-Si/Si1−xGex MOS devices using Monte Carlo simulation

Electron effective mobility in strained-Si/Si1−xGex MOS devices using Monte Carlo simulation

Atomic layer deposition of crystalline SrHfO3 directly on Ge (001) for high-k dielectric applications

Structural characterization of strained silicon grown on a SiGe buffer layer

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