Strategies and Techniques for Optimizing Power in BIST: A Review

Abstract

Power dissipation is a challenging problem in current VLSI designs. In general the power consumption of device is more in the testing mode than in the normal system operation. Built in self test (BIST) and scan-based BIST are the techniques used for testing and detecting the faulty components in the VLSI circuit. Linear Feedback Shift Register (LFSR) in BIST generates pseudo-random patterns for detecting the faults, increasing the power consumption during testing, boosting the need to add power optimizations to BIST pattern generators. This paper identifies the different techniques to modify the BIST architecture thereby finding an optimal choice to reduce power consumption without compromising upon fault coverage.

Design of test generator for embedded self-testing

“…The signature can be analyzed from different perspectives in the coding theory, algebra residual classes, and set theory and graph theory chains. These approaches are not competing because they complement each other [12][13][14][15][16][17][18][19][20][21][22][23][24].…”