Strategies of RC Delay Reduction in 45 nm BEOL Technology

Kawamura, Hiroshi; Ochimizu, H.; Tsukune, A.; Okano, Shun; Naitou, K.; Sakamoto, M.; Takesako, S.; Shirasu, T.; Asneil, A.; Idani, Naoki; Sugimoto, K.; Ozaki, Shiro; Nakata, Yoshihiro; Owada, T.; Watatani, H.; O'Hara, Neal; Ohtsuka, N.; Sunayama, M.; Sakai, Hiroshi; Oryoji, M.; Akiyama, Shin–ichi; Iwata, Hiroshi; Yamamoto, H.; Shimoda, Yoshio; Yao, T.; Suda, Satoshi; Suzuki, Takashi; Sakai, Satoru; Kitada, Hideki; Amari, Saad El; Tabira, T.; Matsuura, Akira; Iba, Yoshihisa; Mizushima, Y.; Matsuyama, Hideya; Suzuki, Yoshiyuki; Yanai, Koji; Nakaishi, Masafumi; Futatsugi, T.; Hanyu, Isamu; Nakamura, Tomoji; Sugii, T.

doi:10.1109/iitc.2007.382383

Cited by 9 publications

(4 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The first is a porogen-based PECVD OSG-2.0 (acronym ALKB) 32 with as-deposited k value of 2.05. The second one is an OSG-2.3 (nanocrystalline silica, acronym NCS) 33 with k ≈ 2.3, synthesized by self-assembling chemistry and spin-on deposition. Compared with OSG-2.0, OSG-2.3 has a lower open porosity and smaller pore size.…”

mentioning

confidence: 99%

Low Damage Cryogenic Etching of Porous Organosilicate Low-k Materials Using SF₆/O₂/SiF₄

Zhang

Ljazouli

Lefaucheux

et al. 2013

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

Low temperature plasma etching of porous organosilicate low-k films is studied, in an ICP chamber with cryo-cooled substrate holder, using Fluorine-based plasma discharges. It is demonstrated that plasma-induced damage is significantly reduced when the base temperature is below a threshold T c that depends on pore size of low-k materials. For T < T c , almost no carbon depletion is observed and the k-value degradation is negligible. It is shown that protection occurs mainly through the condensation of the etch by-products and their ability to seal the open pores against radical diffusion. By addition of SiF 4 and O 2 into the gas discharge, plasma-induced damage is further reduced, as a result of SiO x F y deposition. Vertical trench profiles are obtained in patterned structures, using an inorganic hard mask. The damage reduction mechanism is discussed and a protection model is proposed.

show abstract

mentioning

confidence: 99%

Low Damage Cryogenic Etching of Porous Organosilicate Low-k Materials Using SF₆/O₂/SiF₄

Zhang

Ljazouli

Lefaucheux

et al. 2013

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

show abstract

“…In this study, nano-clustering silica (NCS) was used as a porous low-k film. 9) NCS film has a dielectric constant of 2.25. Sample specimens were prepared by coating 150-nmthick NCS on bare Si wafers and were used to study the lowk damage on the surface directly exposed to plasma.…”

Section: Methodsmentioning

confidence: 99%

Effects of Etch Rate on Plasma-Induced Damage to Porous Low-k Films

Iba

Kirimura

Sasaki

et al. 2008

jjap

View full text Add to dashboard Cite

We investigated the effects of etch rate on low-k damage induced by dry etching under CF 4 , CF 4 /O 2 , and C 4 F 6 /O 2 /Ar chemistry conditions. The amount of damage increases with decreasing etch rate in all chemistries. This is because the amount of fluorine or oxygen radical diffusion increases with plasma exposure time. These radicals extract CH 3 groups from the low-k film or oxidize the film. To reduce damage to the lowest level possible, it is necessary to suppress the effect of the damage diffusion using etching conditions where the etching speed is higher than the diffusion speed of the damage.

show abstract

“…Previously, the switching speed of a semiconductor was a major factor for determining chip speed, but RC delay, resulting from high density metal interconnections, became the more dominant factor for chip speed because of thinner dielectric layers and narrower line spaces. A report on strategies to reduce RC delay in 45nm back-end-of-line (BEOL) supports the trend of semiconductor interconnection technology [5]. With the increased demand of high functionality in mobile electronics, the number of I/O and signal transmission speed became crucial issues in microelectronics devices.…”

Section: Trends Of Microelectronics Manufacturing Techmentioning

confidence: 99%

Hands-On Experience-Based Comprehensive Curriculum for Microelectronics Manufacturing Engineering Education

Ha¹,

Hong²

2016

Transactions on Electrical and Electronic Materials

View full text Add to dashboard Cite

Microelectronic product consumers may already be expecting another paradigm shift with smarter phones over smart phones, but the current status of microelectronic manufacturing engineering education (MMEE) in universities hardly makes up the pace for such a fast moving technology paradigm shift. The purpose of MMEE is to educate fouryear university graduates to work in the microelectronics industry with up-to-date knowledge and self-motivation. In this paper, we present a comprehensive curriculum for a four-year university degree program in the area of microelectronics manufacturing. Three hands-on experienced-based courses are proposed, along with a methodology for undergraduate students to acquire hands-on experience, towards integrated circuits (ICs) design, fabrication and packaging, are presented in consideration of manufacturing engineering education. Semiconductor device and circuit design course for junior level is designed to cover how designed circuits progress to micro-fabrication by practicing full customization of the layout of digital circuits. Hands-on experienced-based semiconductor fabrication courses are composed to enhance students' motivation to participate in self-motivated semiconductor fab activities by performing a series of collaborations. Finally, the Microelectronics Packaging course provides greater possibilities of mastered skillsets in the area of microelectronics manufacturing with the fabrication of printed circuit boards (PCBs) and board level assembly for microprocessor applications. The evaluation of the presented comprehensive curriculum was performed with a students' survey. All the students responded with "Strongly Agree" or "Agree" for the manufacturing related courses. Through the development and application of the presented curriculum for the past six years, we are convinced that students' confidence in obtaining their desired jobs or choosing higher degrees in the area of microelectronics manufacturing was increased. We confirmed that the hypothesis on the inclusion of handson experience-based courses for MMEE is beneficial to enhancing the motivation for learning.

show abstract

Strategies of RC Delay Reduction in 45 nm BEOL Technology

Cited by 9 publications

References 0 publications

Low Damage Cryogenic Etching of Porous Organosilicate Low-k Materials Using SF₆/O₂/SiF₄

Low Damage Cryogenic Etching of Porous Organosilicate Low-k Materials Using SF₆/O₂/SiF₄

Effects of Etch Rate on Plasma-Induced Damage to Porous Low-k Films

Hands-On Experience-Based Comprehensive Curriculum for Microelectronics Manufacturing Engineering Education

Contact Info

Product

Resources

About

Strategies of RC Delay Reduction in 45 nm BEOL Technology

Cited by 9 publications

References 0 publications

Low Damage Cryogenic Etching of Porous Organosilicate Low-k Materials Using SF6/O2/SiF4

Low Damage Cryogenic Etching of Porous Organosilicate Low-k Materials Using SF6/O2/SiF4

Effects of Etch Rate on Plasma-Induced Damage to Porous Low-k Films

Hands-On Experience-Based Comprehensive Curriculum for Microelectronics Manufacturing Engineering Education

Contact Info

Product

Resources

About

Low Damage Cryogenic Etching of Porous Organosilicate Low-k Materials Using SF₆/O₂/SiF₄

Low Damage Cryogenic Etching of Porous Organosilicate Low-k Materials Using SF₆/O₂/SiF₄