Strategy for TSV scaling with consideration on thermo-mechanical stress and acceptable delay

Ghosh, Kaushik; Zhang, Jun; Zhang, L.; Dong, Yuanwei; Li, H.Y.; Tan, Chuan Seng; Xia, Guangrui

doi:10.1109/impact.2012.6420220

Cited by 9 publications

(13 citation statements)

References 5 publications

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“…where γ i T and γ i σ are temperature and stress gradients sensitivity in the ith grid with respect to the dummy TSV density, and are given by ∂T i /∂η i and ∂σ i /∂η i determined from (13) and (14), respectively.…”

Section: A Clock-skew Sensitivity With Respect To Dummy Tsv Densitymentioning

confidence: 99%

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Reliable 3-D Clock-Tree Synthesis Considering Nonlinear Capacitive TSV Model With Electrical–Thermal–Mechanical Coupling

Sai

Shang

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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A robust physical design of 3-D IC requires investigation on through-silicon via (TSV). The large temperatures and stress gradients can severely affect TSV delay with large variation. The traditional physical model treats TSV as a resistor with linear electrical-thermal dependence, which ignores the fundamental device physics. In this paper, a physics-based electricalthermal-mechanical delay model is developed for signal TSVs in 3-D IC. With consideration of liner material and also stress, a nonlinear model is established between electrical delay with temperature and stress. Moreover, sensitivity analysis is performed to relate the reduction of temperature and stress gradients with respect to dummy TSVs insertion. Taking the design of 3-D clock tree as a case study, we have formulated a nonlinear optimization problem for clock-skew reduction. By allocating dummy TSVs to reduce the temperature and stress gradients, the clock skew introduced by signal TSVs and drivers can be minimized. A number of 3-D clock-tree benchmarks are utilized in experiments. We have observed that with the use of dummy TSV insertion, clock skew can be reduced by 61.3% on average when the accurate nonlinear electrical-thermal-mechanical delay model is applied.

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Section: A Clock-skew Sensitivity With Respect To Dummy Tsv Densitymentioning

confidence: 99%

“…In this paper, based on recent measurement results in [6], [8], [10], [12], and [13], a nonlinear electrical-thermalmechanical delay model is developed for 3-D clock-tree design. Further, sensitivity analysis is performed for dummy TSV density with respect to reduction of temperature or stress 0278-0070 c 2013 IEEE gradient.…”

mentioning

confidence: 99%

Reliable 3-D Clock-Tree Synthesis Considering Nonlinear Capacitive TSV Model With Electrical–Thermal–Mechanical Coupling

Sai

Shang

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…The mechanical stress from TSVs also affects the carrier mobilities of drivers on the substrate. Based on the alignment of the transistors and the amount of exerted stress, the carrier mobility varies [74,105,106]. This variation in charge carrier mobility adversely affects the delay of drivers.…”

Section: Mechanical Modelmentioning

confidence: 99%

“…This variation in charge carrier mobility adversely affects the delay of drivers. Variation in carrier mobility due to exerted stress [74,105,106] is given by…”

Section: Mechanical Modelmentioning

confidence: 99%

“…As memory and logic components are spread on the common substrate that is close to a heat-sink, the thermal reliability concern of the integrated high-performance server is relaxed in 2.5D integration. In this chapter, based on recent measurement results in [102,73,74,105,106], a nonlinear electrical-thermal-mechanical coupled 3D TSV and 2.5D TSI delay and power models are developed. However, design of TSI I/O links is one of the challenges to be addressed.…”

Section: Introductionmentioning

confidence: 99%

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2.5D and 3D I/O designs for energy-efficient memory-logic integration towards thousand-core on-chip

Dinakarrao¹

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First and foremost, I would like to express the deepest gratitude to my advisor Prof. Yu Hao, for his invaluable support both in my research and life during all years of my work in NTU. I have been extremely fortunate to work under his supervision and I deeply appreciate his time, patience and support throughout my Ph.D. career. His assistance, constructive comments, and technical insights have always been most helpful in addressing my research issues. He taught me to set high standards for myself and made me realize the importance of global competence. For me, he sets a good example of what a researcher should be like: have enthusiasm towards research, always think out of box, and work hard to solve problems. I would like to express my special thanks to Dr. Yu Mingbin, Dr. Roshan Weerasekera, Prof. Siek Liter, Prof. Tan Chuan Seng, and Prof. Chang Chip-hong, for giving me generous amount of time whenever I needed some help. I also want to thank the Virtus and EEE GPO staff Gek Eng, Dorothy, David Robert, Karen, Chow Kam Wah, Christina, and many others who have been really friendly and patient to help me many times on administrative matters. I would like to express my thanks to my wonderful colleagues,

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Methods to reduce thermal stress for TSV Scaling ∼TSV with novel structure: Annular-Trench-Isolated TSV

Feng

Watanabe

Shimamoto

et al. 2015

2015 IEEE 65th Electronic Components and Technology Conference (ECTC)

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Strategy for TSV scaling with consideration on thermo-mechanical stress and acceptable delay

Cited by 9 publications

References 5 publications

Reliable 3-D Clock-Tree Synthesis Considering Nonlinear Capacitive TSV Model With Electrical–Thermal–Mechanical Coupling

Reliable 3-D Clock-Tree Synthesis Considering Nonlinear Capacitive TSV Model With Electrical–Thermal–Mechanical Coupling

2.5D and 3D I/O designs for energy-efficient memory-logic integration towards thousand-core on-chip

Methods to reduce thermal stress for TSV Scaling ∼TSV with novel structure: Annular-Trench-Isolated TSV

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