Strategy of Microscopic Parallelism for Bitplane Image Coding

Aulí-Llinàs, Francesc; Enfedaque, Pablo; Moure, Juan Carlos; Blanes, Ian; Sánchez, Vı́ctor

doi:10.1109/dcc.2015.19

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B Overview Of Compute Unified Device Architecture (Cuda)1

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Cited by 4 publications

(2 citation statements)

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“…Future work will describe its implementation in a GPU appraising the computational throughput. This paper extends our preliminary work [21] with a sequential version of the algorithm, more experimental data, and a revised and more descriptive text.…”

Section: Introductionmentioning

confidence: 63%

Bitplane Image Coding With Parallel Coefficient Processing

Aulí-Llinàs

Enfedaque

Moure

et al. 2016

IEEE Trans. on Image Process.

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Section: Introductionmentioning

confidence: 63%

Bitplane Image Coding With Parallel Coefficient Processing

Aulí-Llinàs

Enfedaque

Moure

et al. 2016

IEEE Trans. on Image Process.

Self Cite

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“…The employed context formation approach has been devised to reduce both computational load and controlflow divergence. More details on its underlying ideas can be found in [24], [25]. As shown in Fig.…”

Section: B Overview Of Compute Unified Device Architecture (Cuda)mentioning

confidence: 99%

GPU Implementation of Bitplane Coding with Parallel Coefficient Processing for High Performance Image Compression

Enfedaque

Aulí-Llinàs

Moure

2017

IEEE Trans. Parallel Distrib. Syst.

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Abstract-The fast compression of images is a requisite in many applications like TV production, teleconferencing, or digital cinema. Many of the algorithms employed in current image compression standards are inherently sequential. High performance implementations of such algorithms often require specialized hardware like field integrated gate arrays. Graphics Processing Units (GPUs) do not commonly achieve high performance on these algorithms because they do not exhibit fine-grain parallelism. Our previous work introduced a new core algorithm for wavelet-based image coding systems. It is tailored for massive parallel architectures. It is called bitplane coding with parallel coefficient processing (BPC-PaCo). This paper introduces the first high performance, GPU-based implementation of BPC-PaCo. A detailed analysis of the algorithm aids its implementation in the GPU. The main insights behind the proposed codec are an efficient thread-to-data mapping, a smart memory management, and the use of efficient cooperation mechanisms to enable interthread communication. Experimental results indicate that the proposed implementation matches the requirements for high resolution (4K) digital cinema in real time, yielding speedups of 30× with respect to the fastest implementations of current compression standards. Also, a power consumption evaluation shows that our implementation consumes 40× less energy for equivalent performance than state-of-the-art methods.

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