Streaming consistency: a model for efficient MPSoC design

Brand, J.W. van den; Research, NXP; Bekooij, Marco

doi:10.1109/dsd.2007.4341446

Cited by 15 publications

(21 citation statements)

References 11 publications

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“…Our software cache coherence protocol for FIFO communication is different from the protocol presented in [16]. In our protocol it is not required to have all interprocessor communication through FIFO buffers, consequently our protocol for FIFO communication can be applied simultaneously with other variants of our software cache coherence protocol.…”

Section: Figure 6: Put Shared Data In a Certain Cache Waymentioning

confidence: 99%

“…Streaming Consistency targets at the streaming application domain. In [16] also an efficient software cache coherence protocol is proposed. The protocol relies on using FIFO buffers for all interprocessor communication.…”

Section: Related Workmentioning

confidence: 99%

“…In [16] a novel memory consistency model, Streaming Consistency, is proposed. Streaming Consistency targets at the streaming application domain.…”

Section: Related Workmentioning

confidence: 99%

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A tuneable software cache coherence protocol for heterogeneous MPSoCs

Ophelders

Bekooij

Corporaal

2009

Proceedings of the 7th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis

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In a multiprocessor system-on-chip (MPSoC) private caches introduce the cache coherence problem. Here, we target at heterogeneous MPSoCs with a network-on-chip (NoC). Existing hardware cache coherence protocols are less suitable for MPSoCs because many off-the-shelf processors used in MPSoCs do not support these protocols. Furthermore, these protocols typically rely on global visibility and serialization of writes which does not match well with the parallel pointto-point communication provided by a NoC. Therefore, we propose a software cache coherence protocol, which can be applied in a heterogeneous MPSoC with a NoC. The software cache coherence protocol relies on explicit synchronization in the software. More specifically, caches are guaranteed to be coherent according to the Release Consistency model, on top of which we have implemented the standard Pthreads communication library. Heterogeneous MPSoCs with off-the-shelf processors can easily be supported, because processors are only required to provide cache control operations, e.g., clean and invalidate. All cache coherence operations are interruptible and do not impact the execution of tasks on other processors, therefore this protocol is suitable for predictable MPSoCs. Our software cache coherence protocol is implemented on an ARM926EJ-S MPSoC which is mapped on an FPGA. From experiments we conclude that the protocol overhead is low for the applications taken from the SPLASH-2 benchmark set. For these applications we observed a speedup between 1.89 and 2.01 on the two processor MPSoC.

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Section: Figure 6: Put Shared Data In a Certain Cache Waymentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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A tuneable software cache coherence protocol for heterogeneous MPSoCs

Ophelders

Bekooij

Corporaal

2009

Proceedings of the 7th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis

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“…Some work [18,19] has been done on the memory consistency issue in the context of NoC based multi-core systems. Petrot et al [18] explored the reordering of the synchronization and data operations due to the routing scheme, diverse paths, and physical location of the target in the NoC based shared memory multi-processor SoC architectures.…”

Section: B Memory Consistency In Noc Based Multicores Systemsmentioning

confidence: 99%

Realization and Scalability of Release and Protected Release Consistency Models in NoC Based Systems

Naeem

Jantsch

Chen

et al. 2011

2011 14th Euromicro Conference on Digital System Design

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“…A synchronized weak memory model that is tailored towards the streaming application domain, is Streaming Consistency [110]. This model assumes that processes communicate via (circular) buffers.…”

Section: -Various Memory Modelsmentioning

confidence: 99%

Programming models for many-core architectures: a co-design approach

Rutgers¹

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It is unlikely that general-purpose single-core performance will improve much in the coming years. The clock speed is limited by physical constraints, and recent architectural improvements are not as beneficial for performance as those were several years ago. However, the transistor count and density per chip still increase, as feature sizes reduce, and material and processing techniques improve. Given a limited single-core performance, but plenty of transistors, the logical next step is towards many-core.A many-core processor contains at least tens of cores and usually distributed memory, which are connected (but physically separated) by an interconnect that has a communication latency of multiple clock cycles. In contrast to a multicore system, which only has a few tightly coupled cores sharing a single bus and memory, several complex problems arise. Notably, many cores require many parallel tasks to fully utilize the cores, and communication happens in a distributed and decentralized way. Therefore, programming such a processor requires the application to exhibit concurrency. Moreover, a concurrent application has to deal with memory state changes with an observable (non-deterministic) intermediate state, whereas singlecore applications observe all state changes to happen atomically. The complexity introduced by these problems makes programming a many-core system with a single-core-based programming approach notoriously hard.The central concept of this thesis is that abstractions, which are related to (manycore) programming, are structured in a single platform model. A platform is a layered view of the hardware, a memory model, a concurrency model, a model of computation, and compile-time and run-time tooling. Then, a programming model is a specific view on this platform, which is used by a programmer.In this view, some details can be hidden from the programmer's perspective, some details cannot. For example, an operating system presents an infinite number of parallel virtual execution units to the application-details regarding scheduling and context switching of processes on one core are hidden from the programmer. On the other hand, a programmer usually has to take full control over separation, distribution, and balancing of workload among different worker threads. To what extent a programmer can rely on automated control over low-level platform-specific details is part of the programming model. This thesis presents modifications to different abstraction layers of a many-core architecture, in order to make the system as a whole more efficient, and to reduce the complexity that is exposed to the programmer via the programming model. viFor evaluation of many-core hardware and corresponding (concurrent) programming techniques, a 32-core MicroBlaze system, named Starburst, is designed and implemented on FPGA. On the hardware architecture level, a network-on-chip is presented that is tailored towards a typical many-core application communication pattern. All cores can access a shared memory, but as this ...

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Streaming consistency: a model for efficient MPSoC design

Cited by 15 publications

References 11 publications

A tuneable software cache coherence protocol for heterogeneous MPSoCs

A tuneable software cache coherence protocol for heterogeneous MPSoCs

Realization and Scalability of Release and Protected Release Consistency Models in NoC Based Systems

Programming models for many-core architectures: a co-design approach

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