Streamline verification process with formal property verification to meet highly compressed design cycle

Chatterjee, Prosenjit

doi:10.1145/1065579.1065757

Cited by 4 publications

(1 citation statement)

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“…To our knowledge, we are the first to propose and study the application of a theory of refinement for dynamic verification. Our approach addresses several challenges facing industry [10,6,5,9]. First, we target functional correctness.…”

Section: Introductionmentioning

confidence: 99%

An Efficient Runtime Validation Framework based on the Theory of Refinement

Jain¹,

Manolios²

2017

Preprint

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We introduce a new methodology based on refinement for testing the functional correctness of hardware and low-level software. Our methodology overcomes several major drawbacks of the de facto testing methodologies used in industry: (1) it is difficult to determine completeness of the properties and tests under consideration (2) defining oracles for tests is expensive and error-prone (3) properties are defined in terms of low-level designs. Our approach compiles a formal refinement conjecture into a runtime check that is performed during simulation. We describe our methodology, discuss algorithmic issues, and provide experimental validation using a 5-stage RISCV pipelined microprocessor and hypervisor.

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Section: Introductionmentioning

confidence: 99%

An Efficient Runtime Validation Framework based on the Theory of Refinement

Jain¹,

Manolios²

2017

Preprint

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Creating Assertion-Based IP

Foster¹,

Krolnik²

2008

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Assertion-based verification of a 32 thread SPARC™ CMT microprocessor

Turumella

Sharma

2008

Proceedings of the 45th Annual Design Automation Conference

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Exhaustive property checking, design defect isolation and functional coverage measurement are some of the key challenges of design verification. This paper describes how an assertion based approach successfully addressed these challenges for the verification of an enterprise class chip-multi-threaded (CMT) SPARC TM microprocessor. Methodology and experiences are discussed and recommendations are made on how to incorporate this into the design verification process. Experience with using assertion checks for formal verification as well as simulation based verification is presented, which is part of over 100 person year design verification effort.

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Streamline verification process with formal property verification to meet highly compressed design cycle

Abstract: In this paper, I describe a methodology and tool flow for using formal verification effectively to reduce the verification burden in large custom ASIC designs.

Cited by 4 publications

References 0 publications

An Efficient Runtime Validation Framework based on the Theory of Refinement

An Efficient Runtime Validation Framework based on the Theory of Refinement

Creating Assertion-Based IP

Assertion-based verification of a 32 thread SPARC™ CMT microprocessor

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