Stress induced leakage current limiting to scale down EEPROM tunnel oxide thickness

Naruke, K.; Taguchi, S.; Wada, Makoto

doi:10.1109/iedm.1988.32846

Cited by 188 publications

(70 citation statements)

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“…3, Tox and Vthi are process-dependent constants. This intrinsic electric field generates stress-induced leakage current (SILC) [17][18], a weak tunneling current that leaks charge away from the FG.…”

Section: Basics Of Nand Flash Memorymentioning

confidence: 99%

Data retention in MLC NAND flash memory: Characterization, optimization, and recovery

Cai

Luo

Haratsch³

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

235

267

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Abstract-Retention errors, caused by charge leakage over time, are the dominant source of flash memory errors. Understanding, characterizing, and reducing retention errors can significantly improve NAND flash memory reliability and endurance. In this paper, we first characterize, with real 2y-nm MLC NAND flash chips, how the threshold voltage distribution of flash memory changes with different retention age -the length of time since a flash cell was programmed. We observe from our characterization results that 1) the optimal read reference voltage of a flash cell, using which the data can be read with the lowest raw bit error rate (RBER), systematically changes with its retention age, and 2) different regions of flash memory can have different retention ages, and hence different optimal read reference voltages. Based on our findings, we propose two new techniques. First, Retention Optimized Reading (ROR) adaptively learns and applies the optimal read reference voltage for each flash memory block online. The key idea of ROR is to periodically learn a tight upper bound, and from there approach the optimal read reference voltage. Our evaluations show that ROR can extend flash memory lifetime by 64% and reduce average error correction latency by 10.1%, with only 768 KB storage overhead in flash memory for a 512 GB flash-based SSD. Second, Retention Failure Recovery (RFR) recovers data with uncorrectable errors offline by identifying and probabilistically correcting flash cells with retention errors. Our evaluation shows that RFR reduces RBER by 50%, which essentially doubles the error correction capability, and thus can effectively recover data from otherwise uncorrectable flash errors.

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Section: Basics Of Nand Flash Memorymentioning

confidence: 99%

Data retention in MLC NAND flash memory: Characterization, optimization, and recovery

Cai

Luo

Haratsch³

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

235

267

View full text Add to dashboard Cite

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“…However, the oxide thickness has barely scaled over the many Flash technology generations, remaining far away from its theoretical limit, because it was soon realized [70,166,167] that repeated P/E cycles led to degradation of the tunnel oxide characteristics, enhanced leakage and worse retention. The enhanced oxide leakage at low fields after electrical stress is known as stress-induced leakage current, or SILC [168,169]. SILC has been largely studied on capacitors and described in terms of a trap-assisted tunneling (TAT) process through oxide traps [170][171][172][173][174][175][176][177][178][179] (see Figure 17a for a pictorial view of the process), in agreement with experimental evidence [180,181].…”

Section: Retention After Cycling and Silcmentioning

confidence: 53%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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“…Data retention characteristics are determined by two mechanisms: stress-induced leakage currents (SILCs) [1][2][3][4][5] and the release of electrons trapped inside the tunnel oxide (detrapping) [6,7]. By using a tunnel oxide >8 nm, we can avoid SILCs.…”

Section: Introductionmentioning

confidence: 99%

New physical model to explain logarithmic time dependence of data retention in flash EEPROM

Kamohara

Okumura

2008

Applied Surface Science

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Stress induced leakage current limiting to scale down EEPROM tunnel oxide thickness

Cited by 188 publications

References 1 publication

Data retention in MLC NAND flash memory: Characterization, optimization, and recovery

Data retention in MLC NAND flash memory: Characterization, optimization, and recovery

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

New physical model to explain logarithmic time dependence of data retention in flash EEPROM

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