Stress-induced voiding beneath vias with wide copper metal leads

A study of Cu/Low-k stress-induced voiding at via bottom and its microstructure effect

“…Layout effects concerning metal line width, length and via location were found to be considerably relevant to SIV [2]- [3]. Several failure mechanism of SIV were discussed and finite element analysis become an indispensable tool to study and characterize stress component in copper interconnect [4]. In addition, it had been reported that Cu/low-k interfacial stress was highly correlated with sizes of copper macro-geometries and Cu via voiding sites [6].…”

Characteristic of heat affected zone in thin gold wire and dynamic transient analysis of wire bonding for microstructure of Cu/Low-K wafer

“…In the 90 nm process, the copper interconnection was encapsulated by low permittivity intermetal dielectric (IMD) materials which easily soften microstructure of Cu/Low-K layers. Previous researches [1][2][3] experimental illustrated failure modes of interfacial delamination/stress-induced void within the Cu/Low-K IMD layers. Because the complete mechanism of wire bonding process includes z-motion, impact and ultrasonic vibration stages [4], many material properties of gold wire were scarcely realized.…”

Effect of stress migration on electromigration for nano scale advanced interconnects

“…One such approach is to add redundant vias in the metal line. Previous work has shown that employing a parallel configuration of multiple Cu vias helps to improve the robustness of Cu interconnects towards both SM and EM failures [90][91][92].…”

“…13: SM failure at various interconnect lengths, (a) L=1.5μm[23], (b) L=30μm[95] and (c) L=70μm[92]. Void nucleation and subsequent growth occurs due to SM flux, independent of the metal length.The second stressing condition is at 2MA/cm 2 where in (jL)=2000A/cm, such that (jL)≈(jL) c .…”