Stress release for shallow trench isolation by single-wafer, rapid-thermal steam oxidation

Luoh, Tuung; Chen, C.S.; Yang, Lijian; Shih, Hsueh-Hao; Chen, K.C.; Hsueh, Chun‐Hway; Chung, Hun-Sang; Pan, S.C.; Lu, Chih‐Yuan

doi:10.1109/rtp.2002.1039448

Cited by 10 publications

(4 citation statements)

References 8 publications

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“…2, dislocation pit is mainly located at STI corner. Once dislocation pit occurs, and then it easily propagates to the other region [11]. Si atom escaped from original site forms point defect, which leads dislocation and stacking fault.…”

Section: Experiments Results and Discussionmentioning

confidence: 99%

Dislocation-Free Shallow Trench Isolation (STI) Chemical Mechanical Polishing (CMP) Process for Embedded Flash Memory

Kim

Yoo

Chang

2007

SSP

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The ambient and denuded trench top corner at the step of gate oxidation play an important role to generate defect. Furthermore, dislocation-free flash process is proposed, and its mechanism as well. The impact on dislocation of the other processes is also discussed. And we knew that using of dry oxidation for gate oxide has the characteristic to reduce the dislocation. Consequently, the dislocation free wafer is obtained by changing gate oxide from wet to dry in manufacturing embedded flash.

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Section: Experiments Results and Discussionmentioning

confidence: 99%

Dislocation-Free Shallow Trench Isolation (STI) Chemical Mechanical Polishing (CMP) Process for Embedded Flash Memory

Kim

Yoo

Chang

2007

SSP

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“…Most of failure modes are related to dislocation caused by process thermal stress and interaction with ion implantation, or CMP scratch [1]- [3]. In our study, the focus is on crack formation in combination with Cu penetration into silicon [4], resulting in excessive junction leakage current after thermal stress test.…”

Section: Introductionmentioning

confidence: 99%

Cu concentration from backside contamination induced STI crack after High Temperature Stress

Lee

Hsiang

Zimmermann

et al. 2015

2015 IEEE 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits

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This study presents integrated circuit failure analysis (FA) results of reliability fail devices with high pin leakage (UHAST--als a crack along the STI (shallow trench isolation) sidewall and into Si crystallographic plane. Copper (Cu) was found by EDX analysis underneath Ni silicide layer and migrated into silicon STI edge. One main observation was that the Cu crack occurred systematically on a small active area (p-sub) defined as p-well with minimum design rule distance to n-well active area. The source of Cu is investigated in a series of DOE (design of experiments). The article will discuss different hypothesis of Cu contamination during front-end manufacturing and assembly process. A model including layout sensitivity and the thermal stress effect during HTS/UHAST has been provided.978-1-4799-9928-6/15/$31.00 ©2015 IEEE

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“…These low-pressure processes, which are characterized by co-injection of non-combusted oxygen and hydrogen into the process chamber, are commercially available on single wafer RTP, known as ISSG [1,2], as well as on vertical batch furnaces [3]. Superior process properties have been reported like improved STI corner rounding and stress relief [4,5], lattice orientation independence [6] as well as improved leakage and reliability [3]. Efforts have been taken in order to understand and model this new oxidation technique [7].…”

Section: Introductionmentioning

confidence: 99%

A Growth Kinetics Model for the Radical Oxidation of Silicon

Pethe¹,

Hayn²

2008

MSF

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The silicon oxide growth kinetics were investigated for single wafer rapid thermal (RTP) and large batch vertical furnace radical oxidation processes under varying conditions. An oxidation model is proposed in which the oxidation rate of hydrogen–assisted radical oxidation is a combination of constant–rate low pressure wet oxidation and an oxygen radical driven process decaying with increasing oxide thickness. The model parameters for selected RTP and batch furnace oxidation processes are extracted and discussed. The implications of this model are compared to observed properties of the radical oxidation process like lattice orientation, stress independence, bird’s beak formation and thickness uniformity.

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Stress release for shallow trench isolation by single-wafer, rapid-thermal steam oxidation

Cited by 10 publications

References 8 publications

Dislocation-Free Shallow Trench Isolation (STI) Chemical Mechanical Polishing (CMP) Process for Embedded Flash Memory

Dislocation-Free Shallow Trench Isolation (STI) Chemical Mechanical Polishing (CMP) Process for Embedded Flash Memory

Cu concentration from backside contamination induced STI crack after High Temperature Stress

A Growth Kinetics Model for the Radical Oxidation of Silicon

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