Stretching in Time of GaN Active Gate Driving Profiles to Adapt to Changing Load Current

Abstract

Active gate driving, where the gate signal is actively profiled, has been shown to reduce EMI, overshoot, and switching loss, in silicon power converters. Recently, much faster gate drivers with the ability to profile at a 100 ps resolution have been reported, which has opened up the possibility of actively driving emerging wide-bandgap devices. This could allow Gallium Nitride (GaN) and Silicon Carbide (SiC) FETs to be switched faster than is currently possible, as unwanted switching features such as current ringing at turn-on could be eliminated. However, these drivers have previously only been demonstrated with preprogrammed gate profiles that have been optimized at certain operating conditions, whereas converters typically operate in a range of conditions. In this paper, some limitations of using fixed gate profiles on GaN FETs are reported for the first time, and a new method of profile adaptation is demonstrated. First, the gate profiles in a 400 V GaN bridge-leg are optimized to minimize current ringing at turn-on for a given load current. Then, the load current is varied, showing that the gate signal profile remains close to optimal for ±20% changes in current. Also, over a larger range of at least ±35%, the profiled waveform performs better than a non-profiled gate waveform. It is then demonstrated that by slightly reducing the driver's internal clock frequency with increasing load current, the profile is re-optimized for new load currents. It is concluded that driver clock frequency adaptation may be a means of adapting gate profiles to load current variation and possibly also to temperature variation.

Experimental Investigations on the Tuning of Active Gate Drivers under Load Current Variations

“…More precisely, variations of the load current should be careful considered, as they are rather common in practical scenarios. Reference [8] suggests to reduce the clock frequency of the proposed AGD when the load current increases. In [7], both current and temperature variations were investigated, and, a look-up table is proposed to store the AGD profiles for different currents in [9].…”

Gate driver IC for enhancement mode GaN power transistors with senseFET reverse conduction detection circuit

“…Driving an e ‐mode GaN transistor is similar to driving an n‐type silicon power MOSFET but with new challenges. The low threshold voltage (around 1.5 V) and low maximum gate voltage (7 V) narrow the tolerance of safe gate driving voltage window [7], which restricts the maximum d ν /d t and d i /d t due to possible ringing during the turn‐on and turn‐off transitions [8, 9]. The lack of an integrated body diode also leads to large undershoot voltage which increases reverse conduction loss.…”

Optimization Platform to Find a Switching Pattern of Digital Active Gate Drive for Reducing Both Switching Loss and Surge Voltage

“…The fact of high computation cost and time consuming is also reported in [19] when automatic optimization based on simulated annealing was applied. A similar issue in determining the gate drive profile was also addressed in [20]- [22]. A systematic approach to demonstrate the effect of digital active gate drive waveforms on an IGBT switching operation was proposed in [20].…”

“…In [21], the searching time for the optimum gate resistor values is reduced because of less experimental tests, which were followed by an analysis of the measured waveforms and losses. In [22], a profiled optimum gate drive waveform is able to adapt to load current variations using driver frequency adaption. Moreover, [23] reported that the resulting optimal pattern is dependent on circuit stray inductance.…”