STT-MRAM Design Technology Co-optimization for Hardware Neural Networks

Xu, Nuo; Lu, Yang; Qi, Weiyi; Jiang, Zhengping; Peng, Xiaochen; Fan, Chen; Wang, Jing; Choi, Woosung; Yu, Shimeng; Kim, Dae Sin

doi:10.1109/iedm.2018.8614560

Cited by 30 publications

(8 citation statements)

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“…Table IV summarizes the comparison with prior art on in-memory computing architectures based on non-volatile arrays, including the proposed STT-BNN architecture as reported for a 128 × 128 sub-array size. From this table, the maximum achievable classification accuracy of STT-BNN over the MNIST dataset is equivalent to [8], [35] and better than [15] by 3.4%. The work in [8] uses a 3-bit multilevel sense amplifier (i.e., a 3-bit ADC) to push the classification accuracy over the CIFAR-10 dataset at 86.08%, which is 6.07% higher than the proposed STT-BNN.…”

Section: System-level Validation and Comparison With Prior Artmentioning

confidence: 98%

“…As a consequence, most STT-MRAM-based in-memory BNN macros only perform bit-wise operations with two or three operands per memory access, as larger numbers of operands degrade the accuracy of the MAC computation and ultimately the classification accuracy [13], [14], [17], [18]. The macros in [15] and [16] only support 0 or +1 values for activations with the limitations as in [5] and [6].…”

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confidence: 99%

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STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks

Pham

Trinh

Chang

et al. 2022

IEEE J. Emerg. Sel. Topics Circuits Syst.

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This paper presents a novel architecture for in-memory computation of binary neural network (BNN) workloads based on STT-MRAM arrays. In the proposed architecture, BNN inputs are fed through bitlines, then, a BNN vector multiplication can be done by single sensing of the merged SL voltage of a row. Our design allows to perform unrestricted accumulation across rows for full utilization of the array and BNN model scalability, and overcomes challenges on the sensing circuit due to the limitation of low regular tunneling magnetoresistance ratio (TMR) in STT-MRAM. Circuit techniques are introduced in the periphery to make the energy-speed-area-robustness tradeoff more favorable. In particular, time-based sensing (TBS) and boosting are introduced to enhance the accuracy of the BNN computations. System simulations show 80.01% (98.42%) accuracy under the CIFAR-10 (MNIST) dataset under the effect of local and global process variations, corresponding to an 8.59% (0.38%) accuracy loss compared to the original BNN software implementation, while achieving an energy efficiency of 311 TOPS/W.

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Section: System-level Validation and Comparison With Prior Artmentioning

confidence: 98%

mentioning

confidence: 99%

STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks

Pham

Trinh

Chang

et al. 2022

IEEE J. Emerg. Sel. Topics Circuits Syst.

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show abstract

“…However, most of these solutions neither consider the effects of STT-MRAM and CMOS process, voltage and temperature (PVT) variations, nor the RC delay mismatch to validate the computing accuracy; hence they could be highly optimistic about design closures. Existing efforts that do consider these effects mainly focus only on read operations and do not implement CIM-based logic operations [4,10,11]. Moreover, prior work on STT-MRAM based CIM lacks silicon-driven investigations to accurately determine the impact of these non-idealities on the computing accuracy.…”

Section: Introductionmentioning

confidence: 99%

CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out

Singh

Zahedi

Shahroodi

et al. 2022

2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS)

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Spin-torque transfer magnetic random access memory (STT-MRAM) based computation-in-memory (CIM) architectures have shown great prospects for energy-efficient computing. However, device variations and non-idealities narrow down the sensing margin that severely impacts the computing accuracy. In this work, we propose an adaptive referencing mechanism to improve the sensing margin of a CIM architecture for boolean binary logic (BBL) operations. We generate reference signals using multiple STT-MRAM devices and place them strategically into the array such that these signals can address the variations and trace the wire parasitics effectively. We have demonstrated this behavior using STT-MRAM model, which is calibrated using 1Mbit characterization array. Results show that our proposed architecture for binary neural network (BNN) achieves up to 17.8 TOPS/W on the MNIST dataset and 130× performance improvement for text encryption compared to the software implementation on CPU.

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“…29,34,56,58,59,75,[90][91][92][93] lists the recent neural network implementations. Several in-MRAM computing studies were implemented and verified using a 2x nm CMOS process.…”

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confidence: 99%

A survey of in-spin transfer torque MRAM computing

Cai

Liu

Chen

et al. 2021

Sci. China Inf. Sci.

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In traditional von Neumann computing architectures, the essential transfer of data between the processor and memory hierarchies limits the computational efficiency of next-generation system-on-a-chip. The emerging in-memory computing (IMC) approach addresses this issue and facilitates the movement of significant data and rapid computations. Among the different memory types, intrinsic energy efficiency is demonstrated by in-magnetic random access memory (MRAM) computing with a low-power spintronic magnetic tunnel junction device and hybrid integration at an advanced complementary metal-oxide semiconductor node. This study reviews state-of-the-art techniques for managing IMC with an emphasis on spin-transfer torque-MRAM computing via design schemes at the bit-cell, circuit, and system levels. In addition, this study presents effective design techniques and potential challenges and demonstrates the existing limitations of in-MRAM computing and potential methods for overcoming these issues. This study also considers the design technology co-optimization from the IMC perspective.

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STT-MRAM Design Technology Co-optimization for Hardware Neural Networks

Cited by 30 publications

References 0 publications

STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks

STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks

CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out

A survey of in-spin transfer torque MRAM computing

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