Studies on the Performance of Two New Bus Arbitration Schemes for MultiCore Processors

Ramasubramanian, N.; Krishnan, Prabu; Kamakoti, V.

doi:10.1109/iadcc.2009.4809184

Cited by 2 publications

(4 citation statements)

References 4 publications

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“…PLC is modularized by IO module, processor module, power supply module and communication module [3]. Each module is connected by backplane bus and there are several backplane standards like request service based bus and future-bus [4]. Such standards have complex structure and not optimized for home energy control system.…”

Section: Hcec Architecturementioning

confidence: 99%

The implementation of a shared bus architecture for Home Energy Controller

Hyun¹,

Kim

Ham

2012

2012 IEEE International Conference on Consumer Electronics (ICCE)

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For the implementation of green home systems, it is important to control renewable energy generators like wind turbine or solar energy system. It is advantageous to use the PLC for maintaining compatibility with various power systems. In this paper, we present a programmable logic controller (PLC) with a design Multi-input Multi-output (MIMO) bus.The key advantages of proposed MIMO bus is expandable bus architecture and supports packet based data transfer. Proposed MIMO bus is consisted by event bus, data transmit bus and two wired serial bus. As a result, there is advantage in bus throughput compared to general system bus.

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Section: Hcec Architecturementioning

confidence: 99%

The implementation of a shared bus architecture for Home Energy Controller

Hyun¹,

Kim

Ham

2012

2012 IEEE International Conference on Consumer Electronics (ICCE)

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“…Two new bus arbitration algorithms, which are RequestService and Age-Based algorithms are introduced in [2]. The new algorithms try to improve the existing algorithms in term of latency caused by the contention among the bus masters.…”

Section: Related Workmentioning

confidence: 99%

“…5, combines the dynamic lottery algorithm with the age-based algorithm from [2] to generate the ticket values. The ABL gives higher ticket values to masters that have recently won the bus.…”

Section: Age-based Lottery Arbitrationmentioning

confidence: 99%

“…The contention between the processors in CMP systems adds significant overhead in order to manage the access to that shared bus [2]. Thus, scheduling mechanisms or "arbitration schemes", which are employed to synchronize and schedule the bus requesting from different bus masters in order to avoid contentions, have a major and important effect on the overall performance of the CMP design [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

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A Bus Arbitration Scheme with an Efficient Utilization and Distribution

El-Kustaban¹,

Qahtan²

2017

ijacsa

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Abstract-Computer designers utilize the recent huge advances in Very Large Scale Integration (VLSI) to place several processors on the same chip die to get Chip Multiprocessor (CMP). The shared bus is the most common media used to connect these processors with each other and with the shared resources. Distributing the shared bus among the contention processors represents a critical issue that affects overall performance of the CMP. Optimal utilization with fair distribution of the shared bus represents another challenge. This paper introduces a bus arbitration scheme, which is an AgeBased Lottery (ABL) Arbitration that combines the lottery and age-based algorithms to overcome the shared bus challenges. The results show that the developed bus arbitration scheme maximizes the bus utilization and improves the distribution by at least 13.5% with an acceptable latency time comparing to the traditional bus arbitration schemes.

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Studies on the Performance of Two New Bus Arbitration Schemes for MultiCore Processors

Cited by 2 publications

References 4 publications

The implementation of a shared bus architecture for Home Energy Controller

The implementation of a shared bus architecture for Home Energy Controller

A Bus Arbitration Scheme with an Efficient Utilization and Distribution

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