Study of bending-induced strain effects on MuGFET performance

Abstract

The impact of stress induced by biaxial mechanical bending on multiple-gate FET (MuGFET) performance is studied. For relatively low levels of bending-induced surface strain (∼ 0.1%), significant enhancements in the driving current can be achieved and maintained with gate-length scaling. This makes package strain a potentially attractive approach to enhancing MuGFET-based CMOS performance at low cost. For bending-induced strain, the enhancements in electron mobility and (110) hole mobility are well predicted by the piezoresistance model using the coefficients for bulk-Si, but the impact of stress on (100) hole mobility is more complex.

(Invited) Strain-Enhanced Performance of Si-Nanowire FETs

“…This characterization technique evaluates the mobility change ∆µ/µ due to a uniaxial stress, applied by a wafer bending system (Fig.11). Up to now, only few data have been published for MG architectures [33]. The obtained set of PR coefficients (longitudinal π L and transversal π T ) provides an additional insight on the potentiality of strain in complex architecture like Si TG or ΩG NWs [34,35].…”

“…11). Up to now, only few data have been published for MG architectures [33]. The obtained set of PR coefficients (longitudinal π L and transversal π T ) provides an additional insight on the potentiality of strain in complex architecture like Si TG or ΩG NWs [34,35].…”

Bias and geometry dependence of total-ionizing-dose effects in SOI FinFETs

“…The SOI FinFETs used in this experiment were fabricated with gate first scheme on (100) oriented SOI wafer, and the detailed process information can be found in [35][36][37]. The thickness of buried oxide (T BOX ) is 150 nm.…”

Strain effect on mobility in nanowire MOSFETs down to 10nm width: Geometrical effects and piezoresistive model

“…A large collection of piezoresistance coefficients has already been published for MOSFETs with different channel materials (Si, Ge, SiGe, ...) [8], [9], inversion surface orientations ((110), (111), (100) for Si and SiGe [10], [11]) or channel crystallographic orientations [12]. Up to now, only a few data are available for multiple gate MOSFETs [13]- [17], for which the impact of scaled dimensions down to ≈10nm can play a significant role. We present here an experimental study of the strain effect on carrier mobility in both Si NMOS and PMOS Trigate nanowires (NWs), with the evolution of the PR coefficients as a function of the NW width and height.…”