Strain effect on mobility in nanowire MOSFETs down to 10nm width: Geometrical effects and piezoresistive model

Pelloux-Prayer, J.; Cassé, M.; Triozon, François; Barraud, S.; Niquet, Yann-Michel; Rouvière, J. L.; Faynot, O.; Reimbold, G.

doi:10.1109/essderc.2015.7324752

Cited by 4 publications

(2 citation statements)

References 24 publications

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“…Strained-MOSFETs will become an important component for high-speed transistors limited by shrinking process nodes [101]. Pelloux-Prayer et al proposed empirical mobility modeling for FinFETs and fully depleted-silicon on insulator (FD-SOI) silicon transistors [102], [103]. The model includes the geometrical parameters, namely, width and height, of the nano-scale silicon channel on two 10 nmscale transistors.…”

Section: Applicationsmentioning

confidence: 99%

Review: Numerical Simulations of Semiconductor Piezoresistance for Computer-Aided Designs

Sugiura

Matsuda

Nakano

2023

IEEE J. Electron Devices Soc.

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The field of piezoresistance has mainly advanced through experimental research; however, the improved accuracy of simulations and the emergence of new materials have increased the importance of simulations in this field. This review discusses the methods and current topics related to simulations of piezoresistive devices. Advancing simulation modeling will facilitate the computer-aided design of piezoresistive devices, and this review introduces the means of establishing these models by discussing the current studies on simulations and calculations in this field. Two simulation methods currently exist namely, device simulations and first-principles theoretical analysis. This review focuses on numerical simulation approaches for modeling of the piezoresistive effect using the multiphysics simulations of the mechanical and electrical behaviors of piezoresistive materials.

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Section: Applicationsmentioning

confidence: 99%

Review: Numerical Simulations of Semiconductor Piezoresistance for Computer-Aided Designs

Sugiura

Matsuda

Nakano

2023

IEEE J. Electron Devices Soc.

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“…Different studied are already done in this NW devices, in [8][9][10][11][12] the performance of NW with respect to strain on mobility was studied, the low-frequency noise was analyzed in [13,14], crystallographic orientation [10,13,14] and scalability effects [4,8,15] are also studied.…”

Section: Introductionmentioning

confidence: 99%

Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias

Itocazu

Almeida

Sonnenberg

et al. 2019

Semicond. Sci. Technol.

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This paper presents a comparison between nMOS and pMOS Ω-Gate Nanowire for different channel width (W NW ) down to 10 nm as a function of the large back gate bias variation (from +20 to −20 V) experimentally and by simulation. The main digital and analog parameters are analyzed in these devices as threshold voltage, subthreshold swing (SS), transconductance, transistor efficiency, Early Voltage and intrinsic voltage gain for transistor channel width from 220 nm down to 10 nm. It is shown that narrow channel devices (W NW =10 nm) present a small variation on the analyzed parameters as a function of back gate voltage due to stronger electrostatic control between gate and channel considering that they are effectively working like a gate-all-around devices. In general, all the nMOS parameters presents better results compared to pMOS due to the mobility enhancements. For wider devices (W NW =220 nm), it depends on the back interface condition. For a large enough back gate bias that tends to create a back interface conduction (+20 V for nMOS and −20 V for pMOS), the SS degrades from 61 mV dec −1 (W NW =10 nm) to 68 mV dec −1 (W NW =220 nm). However for a large enough back gate bias that induces a non-conduction region (tends to accumulation) at back interface (−20 V for nMOS and +20 V for pMOS) the SS changes from 60 to 62 mV dec −1 at the same W NW range, which is a very acceptable results. Additionally, the drain current (I ON ) and transconductance (linear and saturation regions) increase for this back gate bias condition (tends to accumulation), working almost like a pseudo nanosheet device for these parameters, avoiding also the parasitic conduction at the back interface. However, in spite of the intrinsic voltage gain is almost independent of the back gate bias, it improves of at least 10 dB for narrow devices due to the higher Early voltage and almost similar transistor efficiency than the wider ones.

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Back gate influence on transistor efficiency of SOI nMOS Ω-gate nanowire down to 10nm width

Itocazu

Almeida

Sonnenberg

et al. 2017

2017 32nd Symposium on Microelectronics Technology and Devices (SBMicro)

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Strain effect on mobility in nanowire MOSFETs down to 10nm width: Geometrical effects and piezoresistive model

Cited by 4 publications

References 24 publications

Review: Numerical Simulations of Semiconductor Piezoresistance for Computer-Aided Designs

Review: Numerical Simulations of Semiconductor Piezoresistance for Computer-Aided Designs

Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias

Back gate influence on transistor efficiency of SOI nMOS Ω-gate nanowire down to 10nm width

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