Back gate influence on transistor efficiency of SOI nMOS Ω-gate nanowire down to 10nm width

Itocazu, Vitor T.; Almeida, Luciana O.; Sonnenberg, Victor; Agopian, Paula Ghedini Der; Barraud, S.; Vinet, M.; Faynot, O.; Martino, João Antônio

doi:10.1109/sbmicro.2017.8113021

Cited by 2 publications

(1 citation statement)

References 17 publications

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“…Previous work on back gate bias was done in nMOS SOI Ω-gate NW for analog parameters with V GB range of −20 to 0 V in [16], for transistor efficiency in nMOS SOI Ω-gate NW in [17] and for transconductance in saturation region (gm SAT ), output conductance (g D ) and intrinsic voltage gain (A V ) with V GB range of −20 to +20 V in pMOS SOI Ω-gate NW in [18].…”

Section: Introductionmentioning

confidence: 99%

Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias

Itocazu

Almeida

Sonnenberg

et al. 2019

Semicond. Sci. Technol.

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This paper presents a comparison between nMOS and pMOS Ω-Gate Nanowire for different channel width (W NW ) down to 10 nm as a function of the large back gate bias variation (from +20 to −20 V) experimentally and by simulation. The main digital and analog parameters are analyzed in these devices as threshold voltage, subthreshold swing (SS), transconductance, transistor efficiency, Early Voltage and intrinsic voltage gain for transistor channel width from 220 nm down to 10 nm. It is shown that narrow channel devices (W NW =10 nm) present a small variation on the analyzed parameters as a function of back gate voltage due to stronger electrostatic control between gate and channel considering that they are effectively working like a gate-all-around devices. In general, all the nMOS parameters presents better results compared to pMOS due to the mobility enhancements. For wider devices (W NW =220 nm), it depends on the back interface condition. For a large enough back gate bias that tends to create a back interface conduction (+20 V for nMOS and −20 V for pMOS), the SS degrades from 61 mV dec −1 (W NW =10 nm) to 68 mV dec −1 (W NW =220 nm). However for a large enough back gate bias that induces a non-conduction region (tends to accumulation) at back interface (−20 V for nMOS and +20 V for pMOS) the SS changes from 60 to 62 mV dec −1 at the same W NW range, which is a very acceptable results. Additionally, the drain current (I ON ) and transconductance (linear and saturation regions) increase for this back gate bias condition (tends to accumulation), working almost like a pseudo nanosheet device for these parameters, avoiding also the parasitic conduction at the back interface. However, in spite of the intrinsic voltage gain is almost independent of the back gate bias, it improves of at least 10 dB for narrow devices due to the higher Early voltage and almost similar transistor efficiency than the wider ones.

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Section: Introductionmentioning

confidence: 99%