Study of low temperature and high heat-resistant fluxless bonding via nanoscale thin film control toward wafer-level multiple chip stacking for 3D LSI

Morinaga, Eiji; Oka, Yuichi; Nishimori, Hiroaki; Miyagawa, Haruhiko; Satoh, Ryohei; Iwata, Yoshiharu; Kanezaki, Ryota

doi:10.1109/ectc.2012.6248799

Cited by 4 publications

(2 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…These methods may greatly reduce the temperature required at assembly, and therefore reduce the stress induced by thermal mismatch. Bonding materials reported in the literature include InSn by Morinaga et al [49], AuInSn by Xie et al [50], CuSn by Zhang, Agarwal et al [51,52] and Sakuma et al [53], CuInNi by Sakuma et al [53], etc. Agarwal et al used two relatively low-temperature processes for the CuSn material, TLP and solid metal bonding (SMB).…”

Section: Low-temperature Interconnectionmentioning

confidence: 99%

Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art

Liu

Park

2014

Journal of Electronic Packaging

View full text Add to dashboard Cite

Three-dimensional (3D) packaging with through-silicon-vias (TSVs) is an emerging technology featuring smaller package size, higher interconnection density, and better performance; 2.5D packaging using silicon interposers with TSVs is an incremental step toward 3D packaging. Formation of TSVs and interconnection between chips and/or wafers are two key enabling technologies for 3D and 2.5D packaging, and different interconnection methods in chip-to-chip, chip-to-wafer, and wafer-to-wafer schemes have been developed. This article reviews state-of-the-art interconnection technologies reported in recent technical papers. Issues such as bump formation, assembly/bonding process, as well as underfill dispensing in each interconnection type are discussed.

show abstract

Section: Low-temperature Interconnectionmentioning

confidence: 99%

Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art

Liu

Park

2014

Journal of Electronic Packaging

View full text Add to dashboard Cite

show abstract

“…In recent years, lots of engineers and researches were carried out on manufacturing and characterization of TSV [1,2], bonding method corresponding to bond pair structure [3][4][5], thin wafer handling [6], novel assembly processes [7,8], testing methodologies and reliability of micro-bumps [9] [10]. It is aimed for assessing manufacturability of 2.5 & 3D ICs.…”

Section: Introductionmentioning

confidence: 99%

Micro-bump bondability design guidelines for high throughput 2.5D & 3D IC assemblies

Yeh

Kao

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

View full text Add to dashboard Cite

In this paper, mechanical bonding behaviors of microbumps in 2.5D/3D ICs assembly are studied theoretically. Solder force and spring constant of micro-bumps with different bond pad structures are estimated by using Surface Evolver. Deformations of dies with corresponding flattening distances are evaluated based on flexural theory and threedimensional contact theories. Allowable coplanarity of bond surface or die warpage during both mass reflow and thermal compression bond is developed. Guidelines to ensure successful bond and corresponding structural designs are earned.

show abstract

An Overview of the Development of a GPU with Integrated HBM on Silicon Interposer

Lee

Hung

Cheung

et al. 2016

2016 IEEE 66th Electronic Components and Technology Conference (ECTC)

110

View full text Add to dashboard Cite

Study of low temperature and high heat-resistant fluxless bonding via nanoscale thin film control toward wafer-level multiple chip stacking for 3D LSI

Cited by 4 publications

References 11 publications

Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art

Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art

Micro-bump bondability design guidelines for high throughput 2.5D & 3D IC assemblies

An Overview of the Development of a GPU with Integrated HBM on Silicon Interposer

Contact Info

Product

Resources

About

Study of low temperature and high heat-resistant fluxless bonding via nanoscale thin film control toward wafer-level multiple chip stacking for 3D LSI

Cited by 4 publications

References 11 publications

Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art

Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art

Micro-bump bondability design guidelines for high throughput 2.5D &amp; 3D IC assemblies

An Overview of the Development of a GPU with Integrated HBM on Silicon Interposer

Contact Info

Product

Resources

About

Micro-bump bondability design guidelines for high throughput 2.5D & 3D IC assemblies