An Overview of the Development of a GPU with Integrated HBM on Silicon Interposer

Lee, Chang-Chi; Hung, Chih-Pin; Cheung, Calvin; Yang, Ping-Feng; Kao, C. R.; Chen, Dao-Long; Shih, Meng-Kai; Chien, Chien-Lin Chang; Hsiao, Yu-Hsiang; Chen, Li-Chieh; Su, Michael; Alfano, Michael P.; Siegel, Joe; Din, Julius; Black, Bryan

doi:10.1109/ectc.2016.348

Cited by 110 publications

(18 citation statements)

References 9 publications

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“…Using a two-point correlation function, a two-mode PFC model was developed to simulate a square lattice in two dimensions, corresponding to the {100} crystallographic plane of Cu [22]. The two-mode order parameter ρ is written as follows [22]: ρ =ρ + A cos(qx) + cos(qy) + B cos(qx) cos(qy) (1) where A and B are related to the amplitudes of two sets of density waves and q = 2π/a is related to the lattice constant a. Moreover, the symbol a = 0.25 nm is defined hereinafter as the lattice constant of Cu.…”

Section: Methodsmentioning

confidence: 99%

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Processing-Structure-Protrusion Relationship of 3-D Cu TSVs: Control at the Atomic Scale

Liu

Huang

Conway

et al. 2019

IEEE J. Electron Devices Soc.

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A phase-field-crystal model is used to investigate the processing-structure-protrusion relationship of blind Cu through-silicon vias (TSVs) at the atomic scale. A higher temperature results in a larger TSV protrusion. Deformation via dislocation motion dominates at temperatures lower than around 300 • C, while both diffusional and dislocation creep occur at temperatures greater than around 300 • C. TSVs with smaller sidewall roughness R a and wavelength λ a exhibit larger protrusions. Moreover, different protrusion profiles are observed for TSVs with different grain structures. Both protrusions and intrusions are observed when a single grain is placed near the TSV top end, while the top surface protrudes near both edges when it contains more grains. Under symmetric loading, coalescence of the grains occurs near the top end, and a symmetric grain structure can accelerate this process. The strain distributions in TSVs are calculated, and the eigenstrain projection along the vertical direction can be considered an index to predict the TSV protrusion tendency. INDEX TERMSCopper, interconnections, reliability modeling, through-silicon via, microstructure.

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Section: Methodsmentioning

confidence: 99%

“…Three-dimensional (3D) devices, e.g., stacked high bandwidth memory (HBM) [1], are expected to be developed to keep up with the increasing package density requirements. In realizing 3D packaging, an important idea is to utilize through-silicon via (TSV) technology [2]- [4].…”

Section: Introductionmentioning

confidence: 99%

Processing-Structure-Protrusion Relationship of 3-D Cu TSVs: Control at the Atomic Scale

Liu

Huang

Conway

et al. 2019

IEEE J. Electron Devices Soc.

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“…Building an advanced electronic system using an interposer is considered less complex than native 3D integration [18], [19]. In fact, interposer-based systems are already established in the market, e.g., with the AMD Fiji GPU system [22] or Xilinx's Virtex-7 FPGAs [23].…”

Section: 5d and 3d Integrationmentioning

confidence: 99%

“…Ultimately, the goal is to achieve "plug-and-play integration" of large-scale and heterogeneous systems, as opposed to the traditional, monolithic flow for 2D ICs. In general, chiplets integration has been well-received by both the academia (e.g., see [19], [21], [35]) and the industry, with relevant products and technologies already in the market, e.g., see the AMD Fiji system [22] and Intel's Embedded Multi-Die Interconnect Bridge (EMIB) [36].…”

Section: Chiplets: System-level Ip Integrationmentioning

confidence: 99%

2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets

Nabeel¹,

Ashraf²,

Patnaik

et al. 2020

IEEE Trans. Comput.

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Dedicated, after acceptance and publication, in memory of the late Vassos Soteriou. For the first time, we leverage the 2.5D interposer technology to establish system-level security in the face of hardware-and software-centric adversaries. More specifically, we integrate chiplets (i.e., third-party hard intellectual property of complex functionality, like microprocessors) using a security-enforcing interposer. Such hardware organization provides a robust 2.5D root of trust for trustworthy, yet powerful and flexible, computation systems. The security paradigms for our scheme, employed firmly by design and construction, are: 1) stringent physical separation of trusted from untrusted components, and 2) runtime monitoring. The system-level activities of all untrusted commodity chiplets are checked continuously against security policies via physically separated security features. Aside from the security promises, the good economics of outsourced supply chains are still maintained; the system vendor is free to procure chiplets from the open market, while only producing the interposer and assembling the 2.5D system oneself. We showcase our scheme using the Cortex-M0 core and the AHB-Lite bus by ARM, building a secure 64-core system with shared memories. We evaluate our scheme through hardware simulation, considering different threat scenarios. Finally, we devise a physical-design flow for 2.5D systems, based on commercial-grade design tools, to demonstrate and evaluate our 2.5D root of trust.

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“…• According to the core material: silicon (today), organic (currently considered), or glass substrates (future) [16], [52], [53] • According to the interposer type: fully passive, with embedded components such as microfluidic channels [54], or with active components [8], [20], [21], [55] • According to the mounting approach: one-sided or doublesided die placement, distributed high-power or low-power die allocation [8] • According to the chip design: prefabricated dies stacked onto the interposer (such as the AMD Fiji/Fury GPU with stacked HBM chips [56], [57], [58]) or custom dies designed for specific applications (such as the Xilinx Virtex-7 FPGA [59]) As of today, there are several products with interposer technology available on market, notably the AMD Fiji/Fury GPU [56], [57], [58] and the Xilinx Virtex-7 FPGA [59]. In 2016, CEA Leti demonstrated their second generation 3D-NoC technology [20], [21], which combines a series of small dies ("chiplets") fabricated at the FDSOI 28 nm node and co-integrated on a 65 nm CMOS interposer.…”

Section: Interposer Stacksmentioning

confidence: 99%

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

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Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed the mainstream transition from "classical 2D chips" to such large-scale 3D chips. In this paper, we survey all popular 3D integration options available and advocate that using an interposer as system-level integration backbone would be the most practical for large-scale industrial applications and design reuse. We review major design (automation) challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options. Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in general and the prospects for large-scale and trustworthy 3D chips in particular.

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An Overview of the Development of a GPU with Integrated HBM on Silicon Interposer

Cited by 110 publications

References 9 publications

Processing-Structure-Protrusion Relationship of 3-D Cu TSVs: Control at the Atomic Scale

Processing-Structure-Protrusion Relationship of 3-D Cu TSVs: Control at the Atomic Scale

2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

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