Study of LR-Loading Technique for Low-Power Single Flux Quantum Circuits

Abstract

A single-flux-quantum (SFQ) circuit is thought to be very suitable as a peripheral circuit for superconducting quantum bits (qubits), which can manipulate and detect the qubit state at a temperature state similar to qubits. Even though the power consumption of SFQ circuits is extremely small, it is still sufficient to heat the substrate at a temperature below 1 K. We have investigated and demonstrated low-power SFQ circuits for this application, using the LR-loading technique, which can reduce the static power consumption of the SFQ circuits. Simulation results show that the ratio of the switching speed to the time constant of the bias circuit is important for the stable operation of low-power SFQ circuits. The static power consumption of SFQ circuits can be reduced to the same order as the dynamic power consumption through optimization of the circuit parameters. We have designed and tested a low-power SFQ clock generator using the LR-loading technique and confirmed its stable operation at 4.2 K, where the power consumption is reduced by 93% compared with ordinary biased circuits.

Influence of Magnetic Flux Trapped in Moats on Superconducting Integrated Circuit Operation

“…S UPERCONDUCTING circuits can perform logic operations with extremely high energy efficiency compared to semiconductor CMOS integrated circuits [1], [2]. However, because superconducting circuits such as the single-flux-quantum (SFQ) circuit [3], [4] and its modified versions [5], [6], [7], [8], [9], use the magnetic flux quantum as the information carrier, superconducting circuits are sensitive to external magnetic flux. Magnetic flux trapped inside the superconducting circuit affects the circuit operation [10].…”

High-Speed Operation of an SFQ Butterfly Processing Circuit for FFT Processors Using the 10 kA/cm² Nb Process

“…Research results have shown that a 16-bit butterfly processing circuit using CMOS can operate at a power of 2.17 mW at frequencies of 100 MHz, and the energy per operation is calculated to be 21.7×10 −12 J [13]. By introducing low-power techniques such as LR-biasing, the energy of SFQ circuits can be reduced by a factor of 20, giving SFQ circuits a performance advantage over CMOS circuits by more than two orders of magnitude [14].…”

High-speed demonstration of low-power 1 k-bit shift-register memories using LR-biasing SFQ circuits

“…This reduces the advantage of the SFQ shift-register memories in terms of the low-power consumption if we take into account the cooling cost. In order to reduce the static power consumption of the SFQ circuits, LR-biasing SFQ circuits have been investigated [6,7], where the bias resistances for SFQ circuits are replaced with large bias inductances with small bias resistance. In this study, we developed a low-power SFQ shift-register memory using the LR-biasing technique to show its effectiveness in large-scale SFQ circuits.…”