A single-flux-quantum (SFQ) circuit is thought to be very suitable as a peripheral circuit for superconducting quantum bits (qubits), which can manipulate and detect the qubit state at a temperature state similar to qubits. Even though the power consumption of SFQ circuits is extremely small, it is still sufficient to heat the substrate at a temperature below 1 K. We have investigated and demonstrated low-power SFQ circuits for this application, using the LR-loading technique, which can reduce the static power consumption of the SFQ circuits. Simulation results show that the ratio of the switching speed to the time constant of the bias circuit is important for the stable operation of low-power SFQ circuits. The static power consumption of SFQ circuits can be reduced to the same order as the dynamic power consumption through optimization of the circuit parameters. We have designed and tested a low-power SFQ clock generator using the LR-loading technique and confirmed its stable operation at 4.2 K, where the power consumption is reduced by 93% compared with ordinary biased circuits.

A microprocessor test vehicle was developed for the investigation of asynchronous design methodology for rapidsingle-flux-quantum (RSFQ) circuits. We have designed and implemented a fully asynchronous RSFQ microprocessor, named SCRAM2. The data-driven self-timing (DDST) architecture is used for the design of circuit blocks of the SCRAM2. In order to ensure the logical ordering between the circuit blocks, bit-serial handshaking was adopted. The performance of the handshaking system was enhanced based on the scalable-delay-insensitive (SDI) model. The SCRAM2 is an 8-bit bit-serial microprocessor with three-stage pipelining, with a basic microarchitecture similar to that of our previously designed synchronous microprocessor, CORE1. The estimated average performance of the SCRAM2 is 577 MIPS using a logic simulation. We have implemented all circuit components using the SRL 2.5 kA cm 2 Nb process and confirmed their correct operation. Several operations of the SCRAM2 have been successfully confirmed.

We have designed, fabricated and tested a time-to-digital converter (TDC) using SFQ logic circuits. The proposed TDC consists of two sets of ring oscillators and binary counters, and a coincidence detector (CD), which detects the coincidence of the arrival of two SFQ pulses from two ring oscillators. The advantage of the proposed TDC is its simple circuit structure with wide measurement range. The time resolution of the proposed TDC is limited by the resolution of the CD, which is about 10 ps because it is made by an NDRO cell in this study. The circuits are implemented using NEC 2.5 kA/cm 2 Nb standard process and the CONNECT cell library. We have demonstrated the measurement of the propagation delay of a Josephson transmission line by the TDC with the time resolution of about 10 ps.

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We have designed, fabricated and tested a time-to-digital converter (TDC) using SFQ logic circuits. The proposed TDC consists of two sets of ring oscillators and binary counters, and a coincidence detector (CD), which detects the coincidence of the arrival of two SFQ pulses from two ring oscillators. The advantage of the proposed TDC is its simple circuit structure with wide measurement range in addition to the high resolution and the high sensitivity of the SFQ TDC compared to semiconductor TDCs. The time resolution of the proposed TDC is limited by the resolution of the CD. In order to improve the resolution, we have developed a dynamic AND (DAND) gate, which can detect two simultaneous SFQ signal inputs with high accuracy. It was demonstrated that the time resolution of the TDC using the DAND gate is improved to be ±4 ps.