Study of Multicell Upsets in SRAM at a 5-nm Bulk FinFET Node

Pieper, Nicholas J.; Xiong, Y.; Feeley, A.; Pasternak, John; Dodds, N. A.; Ball, D. R.; Bhuva, B. L.

doi:10.1109/tns.2023.3240318

Cited by 8 publications

(2 citation statements)

References 26 publications

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“…As technology advances and integration levels increase, the issue of multiple-bit upset (MBU) in FinFET devices has become increasingly severe. In experiments on 5 nm FinFET SRAM devices, the proportion of multiple-bit upsets caused by a single particle even exceeded 90%, with a single particle impact triggering up to 28 upset bits [17]. In SRAM layout design, SRAM units along the bitline direction are located in the same well region, while SRAM units along the wordline direction are in different well regions.…”

Section: Introductionmentioning

confidence: 99%

Simulation Study on the Charge Collection Mechanism of FinFET Devices in Single-Event Upset

Zhang,

Guo,

Wang

et al. 2024

Micromachines

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Planar devices and FinFET devices exhibit significant differences in single-event upset (SEU) response and charge collection. However, the charge collection process during SEU in FinFET devices has not been thoroughly investigated. This article addresses this gap by establishing a FinFET SRAM simulation structure and employing simulation software to delve into the charge collection process of FinFET devices during single-event upset. The results reveal substantial differences in charge collection between NMOS and PMOS, and that direct incidence of PMOS leads to the phenomenon of multiple-node charge collection causing SRAM unit upset followed by recovery.

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Section: Introductionmentioning

confidence: 99%

Simulation Study on the Charge Collection Mechanism of FinFET Devices in Single-Event Upset

Zhang,

Guo,

Wang

et al. 2024

Micromachines

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“…These ionized electron-hole pairs are subject to both drift and diffusion. They move throughout the entire semiconductor material and are collected by transistors [4][5][6]. The collected electron-hole pairs produce unexpected transient pulses in circuit nodes [7].…”

Section: Introductionmentioning

confidence: 99%

Machine Learning-Based Soft-Error-Rate Evaluation for Large-Scale Integrated Circuits

Song,

Shao,

Chi

et al. 2023

Electronics

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Transient pulses generated by high-energy particles can cause soft errors in circuits, resulting in spacecraft malfunctions and posing serious threats to the normal operation of spacecraft. For integrated circuits used in space applications, it is necessary to first evaluate soft errors caused by transient pulses. Conventional soft-error-rate evaluation tools are designed to simulate the generation of transient pulses using many accurate models, while the propagation of transient pulses is primarily simulated by circuit-level simulation tools. Due to the limitations of simulation tools, conventional evaluation approaches are limited to the circuit scale. The simulation runtime is unbearable for large-scale integrated circuits. This paper presents an approach for evaluating the soft error rate using machine learning. A back propagation neural network is implemented in the proposed approach. It helps to determine the probability of transient pulse propagation. Compared with the conventional soft-error-rate evaluation results, the proposed approach demonstrates a strong correlation in both trend and magnitude. The average difference between the results obtained using the proposed evaluation method and the experimental results is 23.5%, which is 7.5% higher than that between the results obtained using the conventional evaluation method and the experimental results. Compared to the conventional evaluation method, the proposed approach improves the runtime by an order of magnitude. The proposed approach also benefits the locating of highly sensitive circuit nodes in large-scale integrated circuits. Circuit design and radiation hardening are both useful applications.

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