Study of Near-Surface Stresses in Silicon Around Through-Silicon Vias at Elevated Temperatures by Raman Spectroscopy and Simulations

Abstract

The near-surface stress distribution around Cu through-silicon vias (TSVs) was studied by micro-Raman spectroscopy along with finite-element analysis from room temperature to 100 • C. Temperature-dependent measurements, along with simulations, revealed that the stresses near TSVs can have two components: 1) the preexisting stress before copper filling; and 2) the coefficients of thermal expansion (CTE)-mismatch-induced stress. The CTE-mismatch-induced stress resulted in a mobility change, and a keep-out zone (KOZ) at elevated temperatures was also estimated, where the KOZ was defined as the region with a mobility change larger than or equal to 10%. Higher temperatures were shown to reduce the CTE-mismatch-induced stress component and resulted in the shrinkage of KOZs in Si. The preexisting stress was shown to be significant in a region equal to or larger than the KOZs induced by the CTE-mismatch-induced stress only and should be characterized and considered in the KOZ determination and the circuit design. Index Terms-3-D integrated circuit (IC), keep-out zone (KOZ), mobility, stress, through silicon via (TSV).

On the origins of near-surface stresses in silicon around Cu-filled and CNT-filled through silicon vias

“…Details on the Raman measurements and stress calculations can be found in Ref. [16]. With careful measurements, the error bar of + in our work is estimated to be ±15 MPa [16].…”

“…The details on the stress simulations can be found in Ref. [16]. The Ta barrier layer is 20 nm thick, which is too thin to have any significant impact on the stress distribution, and thus was neglected in the stress simulations.…”

“…Raman spectroscopy-based temperature dependent stress study was used in our recent work on Cu-filled TSVs with 5 to 10 μm in diameter [16,17]. Together with stress simulations, the work provided evidences that the near surface stresses are not only due to the CTE-mismatch effect, but also from the pre-existing stress before the Cu filling [16]. However, in those works, the pre-annealed stress distributions or Cu-etched TSVs were not available for comparisons.…”

Stress Impact of the Annealing Procedure of Cu-Filled TSV Packaging on the Performance of Nano-Scaled MOSFETs Evaluated by an Analytical Solution and FEA-Based Submodeling Technique

“…The protrusion and thermal stress of TSV generally depend on the fabrication and annealing procedure and can generate cohesive and interfacial cracking on TSV [ 12 , 13 , 14 , 15 , 16 ]. Raman spectroscopy is widely used to estimate experimentally the residual stress of Cu TSV and the stress impact on the surrounding wafer [ 17 , 18 , 19 ]. In the fabrication procedure of Cu TSV, the annealing process is a critical step to manage the material characteristics, residual stress and Cu pumping.…”

Assembly Process and Electrical Properties of Top-Transferred Graphene on Carbon Nanotubes for Carbon-Based 3-D Interconnects

“…A technical challenge in existing flip chip bumps and TSVs is the difference in coefficient of thermal expansion (CTE) between copper bump/TSV-filler and its surrounding materials. Due to the relatively large CTE mismatch between silicon (2.3×10 -6 /˚C) and copper (17 × 10 -6 /˚C) [9], [10], Cu-based pillar bumps and TSVs fabricated on Si substrate arises numerous stability and reliability issues during chip operation, especially in fluctuated temperature conditions.…”