Study of Random Dopant Fluctuation Effects in FD-SOI MOSFET Using Analytical Threshold Voltage Model

Rao, Rathnamala; DasGupta, Nandita; DasGupta, Amitava

doi:10.1109/tdmr.2010.2044180

Cited by 34 publications

(8 citation statements)

References 11 publications

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“…The junctionless (JL) device concept with highchannel doping concentration is very encouraging and futuristic; however, it poses severe challenges: 1) threshold voltage (V th ) variability due to random dopant fluctuations (RDFs) [5], [6]; 2) low ON-state current due to high source/drain (S/D) series resistance and poor mobility [4], [7]; 3) increased parasitic capacitances [8]; 4) higher gate workfunction (>5.5 eV) requirement to turn-OFF the device [1]; 5) poor switch-OFF capability that is undesired latch up problem due to impact ionization at high drain bias [9]. Rao et al [10] demonstrated that even in inversion mode (IM) devices the V th fluctuations were mainly caused by RDFs, that is expected to further degrade with variation in channel doping and gate length. Aldegunde et al [6] showed that the JL nanowire transistors have much higher subthreshold variability than their counterpart IM devices of equivalent geometry.…”

Section: Introductionmentioning

confidence: 99%

Potential Benefits and Sensitivity Analysis of Dopingless Transistor for Low Power Applications

Sahu

Singh

2015

IEEE Trans. Electron Devices

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In this paper, we report the potential benefits of dopingless double-gate field-effect transistor (DL-DGFET) designed on ultrathin silicon on insulator film for low power applications. The simulation results show that the proposed device exhibits higher ON current and less sensitivity toward device parameter variation compared with highly doped junctionless (JL) DGFET. The constraints of high metal gate workfunction of JL device are also relaxed using midgap materials as a gate electrode in the DL-DGFETs. Sensitivity analysis shows that the DL-DGFET exhibits least sensitivity to device parameter variation especially gate length due to suppression of short-channel effects. The DL-DGFET also shows lower static power dissipation in OFF state and lower intrinsic delay in ON state. The mixed-mode simulation of 6T-static random access memory cell using DL-DGFET shows impressive read and hold noise margins of 147 and 352 mV at V DD = 0.8 V for ultralow power applications. The possible fabrication process flow of DL-DGFET is also proposed.

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Section: Introductionmentioning

confidence: 99%

Potential Benefits and Sensitivity Analysis of Dopingless Transistor for Low Power Applications

Sahu

Singh

2015

IEEE Trans. Electron Devices

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“…19) An approximately analytical model of σV th in FD-SOI MOSFETs has already been proposed. 20) As is presented, the fluctuations of V th increase with the scaling down of devices, which is mainly caused by RDF in the channel. It was found that V th fluctuation depends on oxide thickness, silicon film thickness, and channel dopant number and position.…”

Section: Introductionmentioning

confidence: 89%

Modeling the threshold voltage variation induced by channel random dopant fluctuation in fully depleted silicon-on-insulator MOSFETs

Zhang

Yang

Jiang

et al. 2018

Jpn. J. Appl. Phys.

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In nanoscale fully depleted silicon-on-insulator (FD-SOI) MOSFETs, the standard deviation of threshold voltage (σVth) caused by random dopant fluctuation (RDF) is an important parameter to predict the performance of transistors and circuits. In this paper, an analytic model of σVth considering both the dopant “number” and dopant “position” fluctuation in channels is proposed. A new model of σVth,num caused by “number” is given and the method of obtaining the “position” influence ratio Rp is discussed in this paper. Moreover, the simulation methods are analyzed in detail. The calculated σVth values in FD-SOI MOSFETs are compared with the Sentaurus TCAD simulation results at different channel lengths, channel doping concentrations, SOI film thicknesses, front gate oxide thicknesses, and buried-oxide thicknesses. The comparison shows that the proposed model matches well with the obtained numerical simulation results.

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“…The analytical threshold voltage model of FD-SOI MOSFET with random dopant fluctuations was demonstrated in [17]. Moreover, The dependence of different device parameters, such as channel length, thicknesses of gate oxide and silicon film on deviation of threshold voltage is studied.…”

Section: Introductionmentioning

confidence: 99%

Variability Analysis of Graded Channel Dual Material-double Gate Strained-silicon MOSFET With fixed Charges

Suddapalli

Nistala

2021

Preprint

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In this paper, variability analysis of graded channel dual material (GCDM) double gate (DG) strained-silicon (s-Si) MOSFET with fixed charges is analyzed with the help of Sentaurus TCAD. By varying the different device parameters, the variability analysis of the proposed GCDM-DG s-Si MOSFET is performed with respect to variations in threshold voltage and drain current as the line edge roughness and fluctuations in random dopant, contact resistance, and oxide thickness are considered. The results confirm that the effect of process variations is severe when the device has fixed charges at oxide interface. Moreover, the proposed GCDM-DG s-Si p-MOSFET has less vulnerable to the effects of line edge roughness, fluctuations in oxide thickness and random dopants in comparison with the proposed GCDM-DG s-Si n-MOSFET.

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Study of Random Dopant Fluctuation Effects in FD-SOI MOSFET Using Analytical Threshold Voltage Model

Cited by 34 publications

References 11 publications

Potential Benefits and Sensitivity Analysis of Dopingless Transistor for Low Power Applications

Potential Benefits and Sensitivity Analysis of Dopingless Transistor for Low Power Applications

Modeling the threshold voltage variation induced by channel random dopant fluctuation in fully depleted silicon-on-insulator MOSFETs

Variability Analysis of Graded Channel Dual Material-double Gate Strained-silicon MOSFET With fixed Charges

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