Potential Benefits and Sensitivity Analysis of Dopingless Transistor for Low Power Applications

Abstract

In this paper, we report the potential benefits of dopingless double-gate field-effect transistor (DL-DGFET) designed on ultrathin silicon on insulator film for low power applications. The simulation results show that the proposed device exhibits higher ON current and less sensitivity toward device parameter variation compared with highly doped junctionless (JL) DGFET. The constraints of high metal gate workfunction of JL device are also relaxed using midgap materials as a gate electrode in the DL-DGFETs. Sensitivity analysis shows that the DL-DGFET exhibits least sensitivity to device parameter variation especially gate length due to suppression of short-channel effects. The DL-DGFET also shows lower static power dissipation in OFF state and lower intrinsic delay in ON state. The mixed-mode simulation of 6T-static random access memory cell using DL-DGFET shows impressive read and hold noise margins of 147 and 352 mV at V DD = 0.8 V for ultralow power applications. The possible fabrication process flow of DL-DGFET is also proposed.

Process variation immune dopingless dynamically reconfigurable FET

“…Moreover, with better gate controllability, SS also gets improved. Further, device performance with variation in T Si , T ox , L s , and L T are summarized in Table I, which shows very less change in the device characteristics with large variation in physical parameters as depicted in previously reported dopingless devices [2], [3].…”

“…As miniaturization approaches towards nano-regime, fabrication of these devices with high concentration gradient (abrupt doping profile at junctions) is raising the complexity as well as cost. In that pursuit, recently, two techniques have been proposed: (a) charge plasma (CP) which employs work function engineering at source and drain electrodes [1]- [3], and (b) polarity-gate (PG) which works on the principle of electrostatic bias as in MOS structures [4]- [6]. In this paper, these techniques are considered to propose a new device that reduces the fabrication complexity as well as immunity towards process variation.…”

Investigation of inversion, accumulation and junctionless mode bulk Germanium FinFETs

“…This quantum device simulation considers other models such as, the band-gap narrowing model, S-R-H recombination with doping dependent models and band-toband tunneling (BTBT) model [17,23]. In ultra-scaled Ge FinFETs, quantum confinement effects (QCE) results in band gap widening and mitigates the BTBT leakage; doping is optimized to prevent source-drain tunneling in our structure [24][25][26].…”

“…We have compared Si and Ge device density of states and band structure too. Junctionless (JL) devices with homogenous source drain doping will be the preferred mode of operation in ultra-scaled logic devices due to the various advantages such as reduced scattering and simpler device fabrication processes [14][15][16][17]. Thus we comprehensively analyzed the JL mode of operation which will serve as a benchmark for future scaled device dimensions.…”

Investigation of laterally single-diffused metal oxide semiconductor (LSMOS) field effect transistor

“…The "n + " source/drain regions and "p + " body contact are formed using the charge plasma concept by using metal electrodes of a specific work function [10,11]. The charge plasma concept is used to realize both low power devices [12][13][14][15][16][17][18][19][20][21][22][23][24][25] and a high power p-i-n diode [26]. We show in this work that LDMOS can also be implemented using the charge plasma principle and consequently reduce the number of thermal steps required during the fabrication.…”