Study of temperature variation on threshold voltage and sub-threshold slope of E $$\delta$$ δ DC MOS transistor including quantum corrections and reduction techniques

Das, Rinkee; Gond, Abhishek Kumar; Sengupta, Sarmista; Sahani, Romio Rosan; Pandit, Soumya

doi:10.1007/s00542-016-2995-z

Cited by 5 publications

(2 citation statements)

References 20 publications

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“…Although a recent research has shown that high temperature compensated voltage reference integrated circuit [1] fabricated by silicon carbide (SiC) material is able to work at up to 300℃ , such high temperatures inevitably have many negative effects. For example, temperature rises can cause gate leakage current [2] and introduce threshold voltage variation in MOS transistors [3]. Moreover, the temperature difference between various parts of the clock tree can exacerbate clock skew [4].…”

Section: Introductionmentioning

confidence: 99%

An Enhanced Thermoelectric Collaborative Cooling System With Thermoelectric Generator Serving as a Supplementary Power Source

Wang

Zhang

Liu

et al. 2021

IEEE Trans. Electron Devices

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Thermoelectric coolers (TECs) are widely used in state-of-the-art thermal management systems. Recently, there is a big trend that is to power TECs using thermoelectric generators (TEGs). Mainstream research efforts focus on attaining a higher figure of merit (ZT) of thermoelectric material, which now faces a great challenge. Alternatively, this paper proposes a different approach to improve the performance of TEC, i.e., integration of a thermoelectric generator (TEG) with a TEC. The TEG converts the collected heat energy into electric current, which reduces the power consumption and enhances the cooling capacity of the TEC. Using different methods of connecting the TEC and TEG, two thermoelectric collaborative cooling systems are proposed. Accurate SPICE models of the two cooling systems are established. Experimental results demonstrate that the discrepancy between the currents flowing through the TEC in the experiments and in the SPICE models is less than 4.8% on average. Based on the verified SPICE models, the proposed TEC-TEG collaborative cooling systems are assessed in terms of power consumption, cooling capacity, coefficient of performance, and cooling efficiency. Compared with a typical Peltier cooling system, the two collaborative cooling systems achieve significant performance improvements.

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Section: Introductionmentioning

confidence: 99%

An Enhanced Thermoelectric Collaborative Cooling System With Thermoelectric Generator Serving as a Supplementary Power Source

Wang

Zhang

Liu

et al. 2021

IEEE Trans. Electron Devices

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“…An EδDC transistor is a device structure proposed by us which is reported to be a low-power, low-cost transistor, suitable for SoC applications with controlled process variability effects due to random discrete dopant effects [12], [13], [14], [15], [16], [17]. In the present work, we derive a physics based local drain current variability model of an epitaxial delta doped channel MOS (EδDC) transistor, caused due to random fluctuation of channel length, attributed to the LER/LWR phenomenon.…”

Section: Outline and Contribution Of Our Workmentioning

confidence: 99%

A Unified Model of Drain Current Local Variability due to Channel Length Fluctuation for an n-channel Eδ DC MOS Transistor

Sengupta

Pandit

2021

Silicon

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A drain current local variability compact model due to random fluctuation of channel length induced by line edge roughness/line width roughness (LER/LWR) is derived here. The random fluctuation of channel length leads to correlated fluctuations of threshold voltage and effective mobility of the current carriers. Therefore, an unified compact model is required to combine all the causes. Our model is based on the principle of propagation of variance. For the model verification purpose, calibrated technology computer aided design (TCAD) simulation platform is extensively used for all possible bias regions and several LER profile parameters. Channel profile optimization is critically studied aiming reduction of I D variability. The model is further extended for SOI (Silicon-on-insulator) transistor and validated with literature data of threshold voltage and on-current variability. Keywords Epitaxial delta doped channel • line edge roughness • channel length fluctuation • propagation of variance • roughness amplitude • correlation length.

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Analysis of Temperature Effect in Quadruple Gate Nano-scale FinFET

Toan

Singh

Maity

2020

Silicon

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Study of temperature variation on threshold voltage and sub-threshold slope of E $$\delta$$ δ DC MOS transistor including quantum corrections and reduction techniques

Cited by 5 publications

References 20 publications

An Enhanced Thermoelectric Collaborative Cooling System With Thermoelectric Generator Serving as a Supplementary Power Source

An Enhanced Thermoelectric Collaborative Cooling System With Thermoelectric Generator Serving as a Supplementary Power Source

A Unified Model of Drain Current Local Variability due to Channel Length Fluctuation for an n-channel Eδ DC MOS Transistor

Analysis of Temperature Effect in Quadruple Gate Nano-scale FinFET

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