Study of the electrical performance of chip-on-board (COB) devices

Suthiwongsunthorn, Nathapong; Kilbey, N.; Cordery, A.

doi:10.1109/tcapt.2003.817639

Cited by 3 publications

(2 citation statements)

References 9 publications

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“…The existing of oxygen content was attributed to humidity. During assembly process, water could be absorbed and later released by the underfill material [5][6][7]. Besides, THB test also provided a high humidity environment.…”

Section: Thb Testmentioning

confidence: 99%

Cu/Ni interface study for bump reliability improvement

Wang

Liu

Hsu

et al. 2013

ASMC 2013 SEMI Advanced Semiconductor Manufacturing Conference

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Under Bump Metallization (UBM) quality is crucial to the reliability of flip chip products. This paper focuses on the failure mechanism that attributed to Temperature Humidity Bias (THB) test. The importance of metal film condition is emphasized, and the effect of voltage bias is discussed. In addition, a detailed experiment on Cu/Ni UBM interface is carried out for THB improvement. The investigation scope contains Cu surface topography and Cu/Ni interface adhesion. Based on the experiment results, the optimal process condition has been determined. A notable improvement of THB performance is achieved after process optimization.

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Section: Thb Testmentioning

confidence: 99%

Cu/Ni interface study for bump reliability improvement

Wang

Liu

Hsu

et al. 2013

ASMC 2013 SEMI Advanced Semiconductor Manufacturing Conference

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show abstract

“…would change, however this is still applicable to direct chip attach (DCA) and wafer scale packaging (WSP). Both of these approaches are being actively investigated as methods for attaching the integrated circuit directly to a PCB in order to reduce packaging and assembly costs and increase chip performance [4] [5].…”

Section: Pcb Substrate Vs Carrier Substratementioning

confidence: 99%

Modeling and simulation of packaging substrate effects on radio frequency integrated circuits

Benedik

Ren

2012

2012 IEEE National Aerospace and Electronics Conference (NAECON)

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In this paper an analysis of the effects of integrated circuit packaging substrates on a radio frequency (RF) IC is presented. At RF frequencies the effects of packaging parasitics become crucial when assembling an RF system in package (SiP) or integrating a single die with a package. A differential buffer, which had been previously fabricated in a 90nm CMOS process is used as a vehicle to analyze the effects of packaging on performance. The integration of the buffer die with the package is modeled and analyzed.

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2009 Index IEEE Transactions on Components and Packaging Technologies Vol. 32

2009

IEEE Trans. Comp. Packag. Technol.

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Study of the electrical performance of chip-on-board (COB) devices

Cited by 3 publications

References 9 publications

Cu/Ni interface study for bump reliability improvement

Cu/Ni interface study for bump reliability improvement

Modeling and simulation of packaging substrate effects on radio frequency integrated circuits

2009 Index IEEE Transactions on Components and Packaging Technologies Vol. 32

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