Study on Board Level Drop Reliability of Wafer Level Chip Scale Package with Leadfree Solder

Abstract

However, its board level reliability is a great concern after Wafer level chip scale package (WLCSP) is a promisin board assembly for real application '4]. Unlike FBGA with a p BT substrate as interposer, WLCSP i.e. silicon chip directly packaging technology to accommodate the demand for small, asebe nPBbad ne eprtr aito portable handheld electronic. This bare-die bumped package is assemb ledo PCr or. Under .teer viaion .. . . ... (~~~~thermal cycle) large GTE mismatch between silicon and able to offer significant area savings, improve package . y '.able to offer significant area savings, improve packae rPCB material will cause cracks in solder interconnection. electrical parasitics and power dissipation performance over substrate-based BGA packages. However, its board level eWhile under mechanical or dynamic loadng e.g. drop impact reiailt eseial mehnia performance undershoc usually seen in handheld electronics, difference of stiffness reimaciity ispagrecatlyconcrnfhandheld lectrfor nics unders between silicon and PCB will also lead to cracking in solder interconnection. This is one of the reasons that WLCSPIn this paper, daisy chained WLCSP packages with application is still limited to small chip size. As the conversion leadfree solder bumps have been assembled on customer from SnPb to Pb free solder, the concern on thermal cycling is boards, and board level drop test has been carried out on a eased in a certain extent, as leadfree solder alloy e.g. JEDEC compatible drop tester. First failure is found at 42 SnAg4.OCuO.5 (SAC405) shows good thermal cycling drops among 36 samples. All the electrical failure found is performance. But with this leadfree alloy, the drop caused by the breakage of Cu trace under critical corner ball at performance is reduced as the premature interfacial cracking is PCB side. To understand the failure mechanism and built up seen at solder/metal interface during drop impact. Thus the life prediction model for WLCSP, finite element WLCSP under shock impact is a great concern for application simulation has been carried out by explicit dynamic software ANSYS/LS-Dyna. Strain-rate dependent elastoplastic model hheld eleronics.for solder isdeveloped vi nano-indentation test an There are several types of bump structures for WLCSP.simusolderisdevelopedvianano-indentation.Hig est in.nd Fig. 1 shows 2 typical structures, i.e. direct bump on Al pad implemented to the simulation.Highestinterfacepeeling (BoP) and bump on Cu redistribution layer (RDL). It is stress iS found at one of the corner and between solder anad stres isfoud atoneof te cmer nd etwen slderand important to understand the drop performance for the different PCB Cu pad, which is exactly correlated with failure location imp tunest from the test results. This failure mode is different from those bump structures.results for WLCSP open publications, where failure mostly happened at component side. From simulation analysis, it is understood that the maximum stress located at PCB side is mainly due to the Cu trace connected to the Cu pad...