Study on bond pad damage issue in bare Cu wire bonding on SMOS8MV wafer technology

Zong, Fei; Zhou, Naikuo; Niu, Jiyong; Sun, Zhi‐Wei

doi:10.1109/icept.2015.7236554

Cited by 4 publications

(3 citation statements)

References 18 publications

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“…IMD layers have been highlighted as the weakest structure of pad layout by numerical model 14 and process characterization. 3 The mentioned correlation with literature outcomes enforces the proposed methodology which would experimentally reproduce the mechanical stress induced by wire bonding process. Nanoindentation allows to replicate the mixed energetic and the thermo-mechanical condition of wire bonding process with the advantage of a controlled load in terms of energy, displacement or force.…”

Section: Pad a And B Simulation Results And Experimental Correlationmentioning

confidence: 53%

“…Due to the brittleness of the oxide dielectric layers, the application of an external mechanical load such as the wire bonding process could represent a serious risk of the entire die mechanical integrity. [1][2][3][4] Considering the continuous trend of reducing the device thickness to improve the on-resistance electrical behaviour, several structural options have been proposed. A solution consists in using a soft material interposed in the metal stack 5,6 or in the use of a thicker final metal layer to prevent the mechanical issue related to the device top side.…”

Section: Introductionmentioning

confidence: 99%

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Structural characterization of semiconductor multi-layer pad

Calabretta

Sitta

Oliveri

et al. 2021

Proceedings of the Institution of Mechanical Engineers, Part C:

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Structural mechanics and mechanical reliability issues are becoming more and more challenging in the semiconductor industry due to the continuous trend of the device dimensional shrinkage and simultaneous increased operative temperature and power density. As main consequence of the downsizing and more aggressive operative conditions, the mechanical robustness assessment is now having a central role in the device engineering and assessment phase. The risk of mechanical crack in the brittle oxide layers, which are embedded in pad stacks, increases during the device manufacturing processes such as the electrical wafer testing and during wire bonding. This risk increases with the presence of intrinsic mechanical stress in individual layers resulting from the metal grain growth mechanisms, the stack layers’ interfacial mismatches in coefficients of thermal expansion and the temperature stress induced by doping diffusion and film deposition. The current trend of innovation in the electronic industry is going over the semiconductor material itself and it is now impacting the improvement of the Back-End of Line. Key actors are becoming the interactions between the semiconductor die and the device packaging such as adhesion layers, barriers and metal stacks. In the present work, different pad structures have been structurally analyzed and benchmarked. The experimental characterization of the pad structures has been done through a flat punch nano-indentation to investigate on the mechanical strength and the crack propagation. The considered mechanical load reproduces the vertical impact force applied during wire bonding process to create the bond-pad electrical interconnection. The obtained testing results have been compared to finite element models to analyze the stress distribution through the different layers’ stacks. Scope of this work is to demonstrate the validity of the proposed integrated numerical/experimental methodology, showing the impact of the metal connections layouts by the analysis of the stress notch factors and crack propagation behaviour.

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Section: Pad a And B Simulation Results And Experimental Correlationmentioning

confidence: 53%

Section: Introductionmentioning

confidence: 99%

Structural characterization of semiconductor multi-layer pad

Calabretta

Sitta

Oliveri

et al. 2021

Proceedings of the Institution of Mechanical Engineers, Part C:

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“…Tolerance control is fundamental for improving yield and lowering manufacturing costs. 6 Moreover, the automotive market demands advanced tools to minimize risks during manufacturing flows. 7 For power semiconductor device packages, examples of process optimization involve molding encapsulation processes to improve the compactness of a flip-chip package 8 or the optimization of heatsink assembly methods for effective heat dissipation, which is influenced by the flatness of power packages and heatsinks.…”

Section: Introductionmentioning

confidence: 99%

Warpage modeling for semiconductor power module manufacturing flow improvement

Calabretta

Sitta

Rundo

et al. 2023

Proceedings of the Institution of Mechanical Engineers, Part B:

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The hybrid and battery electric vehicle market is heavily increasing the demand for semiconductor power modules. The manufacturing of such products is more complex than discrete devices. Some parameters, such as module deformation (warpage), play a major role. Power modules have to comply with customer Geometric Dimensioning & Tolerancing (GD&T) targets in order to avoid coolant leakage during operation and to guarantee mechanical compatibility with the driving board. Compliance with an appropriate flatness tolerance reduces rejects during manufacturing processes such as ultrasonic welding, and the consequent impact on reliability. Due to these requirements, there is a need to implement dedicated countermeasures during manufacturing flows and to develop the proper methodologies to monitor flatness tolerances. Appropriate component selection at the design stage also limits flatness through the prediction of deformations during assembly flows using finite element model. This activity outlines the manufacturing flow for a direct cooled semiconductor power module and presents a method for product optimization in terms of flatness tolerance using a dedicated finite element model that calculates the warpage deformation induced by baseplate soldering and different ceramic substrate layouts. Furthermore, we describe experimental methodologies for measuring power module flatness and straightness across the manufacturing phases. Dedicated experiments were conducted for methodological and design validation.

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