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Purpose -The purpose of this paper was to attempt to confirm the root cause of unstable stitch pull strength in PQFN package and propose some permanent solutions for it. Design/methodology/approach -A screen experiment was designed to find the key process out of the manufacturing flow; a non-destructive detaching method and cross section polishing were used to inspect the bond integrity; Auger analysis assisted with argon ion sputter was tried to confirm the contamination; finally the manufacturing processes were redesigned to prevent the contamination. Findings -Some first aids of process optimization got little improvement; the screen experiment of processes found solder die bonding was the one resulted into a poor bond integrity which was demonstrated by non-destructive detaching method and cross section inspection; Auger analysis assisted with argon ion sputter detected that there was a tin layer thicker than 20 nm coated on the bonding surface and the wire bondability of gold wire on this tin coating was poor; the lead frame was redesigned to prevent the wetting and flowing of tin and got a perfect performance. Research limitations/implications -Because of the limitation of time and resources, the proposed solutions for this issue could be studied more deeply. Originality/value -This paper set up an example how to find out the root cause from the complex manufacturing process flow and put forward a quick solution accordingly for the issue.

Delamination was a critical failure to the microelectronics products, and it was introduced mainly by two factors: strong interface stress or poor interface adhesion. In this paper a tracking experiment confirmed the delamination between die attach and leadframe flag in a SOIC device, which occurred during wire bonding. Results of actual experiments and FEA found during the process flow, there were changes of structure profile as well as von Mises stress at the edge of die attach layer. This alternating stress was introduced by temperature cycling during D/A curing, wire bonding and following cooling; and resulted into the delamination at the interface, whose occurrence could be reduced when a higher peak temperature of D/A curing, a lower temperature of wire bonding, a thicker BLT or a CTE-lower die attach was applied. With a balance between delamination and other items, a final solution was proposed and got perfect results. InformationDue to the demands of higher integration level, higher power and lower cost in electronics industry, packaging technology and materials faced more and more challenges. Delamination was one common and critical failure, which may bring great destroys to the package [1-5]; such as die crack, wire bond lift or break, thermal and electrical performance degradation. If all interfaces in the package had perfect adhesions and the stresses were small, delamination was unlikely to occur. However, CTE mismatches between material couples, improper package structures, un-optimized process settings and extreme application environment with humidity or temperature cycling may result into strong interface stresses and package delamination [5][6][7][8][9][10][11][12][13].Some researchers used the method of finite element analysis (FEA) to predict the occurrence of delamination under different conditions. Interface shear stress or strain, von Mises stress, J-integrate and energy release rate were usual indicators to assess the delamination [5,[7][8][9][10][11]14]. While there were few papers about the effects of processes prior to molding on package delamination. This paper focused on the package delamination occurring before molding at the interface between die attach and leadframe flag. The results of actual experiments and FEA found the alternating interface stress, introduced by CTE mismatch and temperature cycling prior to molding, resulted into this delamination. At the same time, effects of some process factors were studied and a final solution was proposed to solve this delamination. BackgroundDuring the characterization of one small outline 28ld non exposed pad device, the package delamination between die attach and leadframe flag was found with through-scan CSAM

Purpose -The purpose of this paper was to attempt to confirm the root cause of wafer damage issue by heavy Al wire wedge bonding and propose some permanent solutions for it. Design/methodology/approach -The infra red-optical beam-induced resistance change (IR-OBIRCH) analysis defines the position of an abnormal hotspot. A cross section and an scanning electron microscope (SEM) confirmed the wafer damage issue and its position. Based on the position of wafer damage, the wedge tool with different life and Al buildup was checked found to be on the wedge tool. Finite element analysis (FEA) modeling analysis and simulation experiment guarantee the Al buildup, and low wedge deformation thickness (WDT) can cause the wafer damage issue. Finally, design of experiment (DOE) experiments are designed to optimize wedge tool dimension and wedge-bond parameters to eliminate wafer damage issue. Findings -Wafer damage issue caused the Vpwr-OUTPUT leakage issue by IR-OBIRCH analysis. Al buildup was found on wedge tool with different life and its size gets larger along with the increase in wedge tool life. Low WDT and bigger Al buildup can cause the wafer damage. Designing new wedge tool and parameters optimization can increase WDT. Research limitations/implications -Because of the limitation of time and resources, finite element method (FEM) modeling and wedge tool dimension could not be studied more deeply. Originality/value -This paper sets an example on how to find out the root cause of wafer damage by a step-by-step analysis and put forward a quick solution accordingly for the issue.

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