Effects of alternating thermal stress on delamination between die attach and leadframe in SOIC package

Abstract

Delamination was a critical failure to the microelectronics products, and it was introduced mainly by two factors: strong interface stress or poor interface adhesion. In this paper a tracking experiment confirmed the delamination between die attach and leadframe flag in a SOIC device, which occurred during wire bonding. Results of actual experiments and FEA found during the process flow, there were changes of structure profile as well as von Mises stress at the edge of die attach layer. This alternating stress was introduced by temperature cycling during D/A curing, wire bonding and following cooling; and resulted into the delamination at the interface, whose occurrence could be reduced when a higher peak temperature of D/A curing, a lower temperature of wire bonding, a thicker BLT or a CTE-lower die attach was applied. With a balance between delamination and other items, a final solution was proposed and got perfect results. InformationDue to the demands of higher integration level, higher power and lower cost in electronics industry, packaging technology and materials faced more and more challenges. Delamination was one common and critical failure, which may bring great destroys to the package [1-5]; such as die crack, wire bond lift or break, thermal and electrical performance degradation. If all interfaces in the package had perfect adhesions and the stresses were small, delamination was unlikely to occur. However, CTE mismatches between material couples, improper package structures, un-optimized process settings and extreme application environment with humidity or temperature cycling may result into strong interface stresses and package delamination [5][6][7][8][9][10][11][12][13].Some researchers used the method of finite element analysis (FEA) to predict the occurrence of delamination under different conditions. Interface shear stress or strain, von Mises stress, J-integrate and energy release rate were usual indicators to assess the delamination [5,[7][8][9][10][11]14]. While there were few papers about the effects of processes prior to molding on package delamination. This paper focused on the package delamination occurring before molding at the interface between die attach and leadframe flag. The results of actual experiments and FEA found the alternating interface stress, introduced by CTE mismatch and temperature cycling prior to molding, resulted into this delamination. At the same time, effects of some process factors were studied and a final solution was proposed to solve this delamination. BackgroundDuring the characterization of one small outline 28ld non exposed pad device, the package delamination between die attach and leadframe flag was found with through-scan CSAM

Effect of Epoxy Molding Compound Material and Roughness Leadframe to Integrated Circuit Package for Automotive Devices

“…In particular, QFNs used for the engine management or under the hood [7] strongly require highly reliable performance and without defects including delamination since the area under the hood generates high temperature, which directly influences the quality and reliability of the QFN package [8]. Delamination is the main problem for IC packaging [9][10][11][12][13][14] including QFN due to the mismatch in the coefficient of thermal expansions between dissimilar materials, leading to delamination and affecting the product quality [15][16][17][18][19]. The adhesion between the leadframe and epoxy molding compound interfacing is a major factor that affects the quality of the product in terms of the delamination [20][21][22].…”