Study on Garbage Collection Schemes for Flash-Based Linux Swap System

Ko, Sohyang; Jun, Seonsoo; Kim, Ki-Yong; Ryu, Yeonseung

doi:10.1109/asea.2008.55

Cited by 8 publications

(3 citation statements)

References 7 publications

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“…For comparison, we have also evaluated two previous schemes: the greedy algorithm and the wear‐aware algorithm. Our evaluation test, by contrast, gives three states of the flash memory schemes: ZWR scheme, flash memory of the greedy algorithm scheme (FGA) , and flash memory of the wear‐aware algorithm scheme (FWA) .…”

Section: Evaluation Methodologymentioning

confidence: 99%

ZWR: Combining wear‐leveling with reclamation for flash‐memory‐based storage systems of embedded systems

Yang

Sandeep

2017

IEEJ Transactions Elec Engng

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Flash memory is widely adopted in embedded applications since it has several unique advantages. However, due to its hardware characteristic, uneven erasing and inefficient reclamation have been major concerns. These may not only severely degrade the overall performance but also damage the reliability. In order to solve these problems, we propose a novel scheme, which we call ZWR, for zoning, wear-leveling, and reclamation. The storage zone is divided into the following three levels: an active zone for storing hot data, an inactive zone for storing cold data, and a transitional zone for storing the reclamation block. A function layer and a flash transformation layer are added to flash memory, which are located between the memory technology device layer and the file system. According to the combined wear-leveling and efficient reclamation, in the function layer, the erase-write cycles are evenly distributed around the entire flash devices and the invalid blocks can be reclaimed properly. Finally, we implement an accurate flash simulator to evaluate the efficacy of ZWR and compare it with those of other flash schemes. We demonstrate that ZWR can effectively solve uneven erasing and inefficient reclamation problems. It can also greatly prolong the service life of flash devices and improve the efficiency of the erasing operation of blocks.

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Section: Evaluation Methodologymentioning

confidence: 99%

ZWR: Combining wear‐leveling with reclamation for flash‐memory‐based storage systems of embedded systems

Yang

Sandeep

2017

IEEJ Transactions Elec Engng

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“…A thorough study on exploiting data compressibility to improve the lifetime is presented in [26]. Efficient garbage collection policies are studied to reduce the relocations of valid pages when reclaiming invalid pages [22]. Wear leveling techniques [20,36] ensures that the full erase cycles of every flash block are exploited so as to avoid a device failure due to some blocks being worn out earlier.…”

Section: Extending An Ssd's Lifetimementioning

confidence: 99%

An efficient page-level FTL to optimize address translation in flash memory

Zhou

Huang

et al. 2015

Proceedings of the Tenth European Conference on Computer Systems

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Flash-based solid state disks (SSDs) have been very popular in consumer and enterprise storage markets due to their high performance, low energy, shock resistance, and compact sizes. However, the increasing SSD capacity imposes great pressure on performing efficient logical to physical address translation in a page-level flash translation layer (FTL). Existing schemes usually employ a built-in RAM cache for storing mapping information, called the mapping cache, to speed up the address translation. Since only a fraction of the mapping table can be cached due to limited cache space, a large number of extra operations to flash memory are required for cache management and garbage collection, degrading the performance and lifetime of an SSD. In this paper, we first apply analytical models to investigate the key factors that incur extra operations. Then, we propose an efficient page-level FTL, named TPFTL, which employs two-level LRU lists to organize cached mapping entries to minimize the extra operations. Inspired by the models, we further design a workload-adaptive loading policy combined with an efficient replacement policy to increase the cache hit ratio and reduce the writebacks of replaced dirty entries. Finally, we evaluate TPFTL using extensive trace-driven simulations. Our evaluation results show that compared to the state-of-the-art FTLs, TPFTL reduces random writes caused by address translation by an average of 62% and improves the response time by up to 24%.

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“…The cleaning cost is the total access time required to erase the victim blocks which includes several reads and writes accessing time (depending on the block utilization levels) plus the erasure time. In short, it can be simplified as in Equation 1 [17]. Block utilization is the ratio between valid pages and total pages.…”

Section: Semi-automatic Cleaningmentioning

confidence: 99%