Study on single-event burnout of SiC VDMOSFET: failure mechanism and influence factors

Li, Qiumei; Chen, Xianping; Luo, Houcai; Li, Xiandong; Ma, Xin; Tao, Lu‐Qi; Qian, Jing; Tan, Chunjian

doi:10.1109/icept47577.2019.245733

Cited by 7 publications

(3 citation statements)

References 13 publications

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“…Based on this structure, a two-dimensional model was constructed in TCAD. The simulation parameters were obtained from previously published papers [11,12,27,28], as shown in Table 2. In the simulation, the incident position of the heavy ions was located above the JFET region, which is the most sensitive area of the oxide.…”

Section: Degradation Mechanism Of Oxide Reliabilitymentioning

confidence: 99%

Oxide Electric Field-Induced Degradation of SiC MOSFET for Heavy-Ion Irradiation

et al. 2023

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This work presents an experimental study of heavy-ion irradiation with different particle linear energy transfer (LET), gate biases, and drain biases. The results reveal that when the irradiation biases are low, the SiC MOSFET does not experience single event effect (SEE) and the electrical properties remain unchanged (the devices are in the safe operating area (SOA)). However, the oxide breakdown voltage of the device is significantly decreased due to the latent damage generated by the irradiation. The experimental results, along with TCAD simulations, suggest that the latent damage induced by the irradiation in the gate oxide is closely related to the peak electric field in the gate oxide at the time of particle incidence. This peak electric field is determined by the potential difference between the two sides of the gate oxide, which is affected by the particle LET, gate biases, and drain biases together. The high potential is determined by the combined effect of the LET and the drain-source voltage. The impact ionization of the particle by the applied electric field causes the accumulation of holes in the JFET oxide, which leads to a decrease in the doping of the N− epitaxial layer and eventually causes a rise in the high potential near the JFET oxide. The low potential is determined by the gate bias, and the negative bias applied to the gate can further increase the potential difference between the two sides of the oxide, causing an increase in the peak electric field in the gate oxide and aggravating the gate oxide damage.

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Section: Degradation Mechanism Of Oxide Reliabilitymentioning

confidence: 99%

Oxide Electric Field-Induced Degradation of SiC MOSFET for Heavy-Ion Irradiation

et al. 2023

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“…The structure and doping of the device in the TCAD simulations are derived from published articles. 9,[24][25][26][27] Aiming at the different electric field distributions of the device under different gate biases and drain biases, the potential distribution in the device is simulated by TCAD. Figure 5(a) shows the potential distribution in the unirradiated device when V DS = 200 V and V GS = −5 V, which is the worst bias in this work.…”

Section: Tcad Simulationmentioning

confidence: 99%

Study of heavy ion induced single event gate rupture effect in SiC MOSFETs

Liang

Feng

et al. 2022

Jpn. J. Appl. Phys.

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Single Event Gate Rupture(SEGR) is one of the most severe problems that SiC MOSFETs experience in the space radiation environment. The influence of drain bias (VDS) and gate bias (VGS) on Single Event Gate Rupture was explored in this work using the fluctuation of leakage current when the device was irradiated at various biases. The source of leakage current is isolated and determined through testing, and the influence mechanisms of VGS and VDS effects on SEGR are further explored using TCAD simulation. The investigation demonstrates that while the drain bias can indirectly enhance the potential of SiC-side oxide, the gate bias can directly alter the potential of metal-side oxide during heavy ion irradiation. When gate bias and drain bias are combined, a strong electric field is generated in the gate oxide, resulting in SEGR in SiC MOSFETs. SEGR effect is a significant issue for SiC MOSFETs.

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“…The SEB mechanisms have gradually gained more and more interest over the past few years in the context of parasitic bipolar junction transistor turn-on mechanisms, their contributions to SEB having been reported in several studies [ 5 , 18 ]. Nonetheless, in contrast to silicon power devices, research studies on SEE and the mechanism of SiC VDMOS are relatively few; in general, such extensive research is essential and worthwhile.…”

Section: Introductionmentioning

confidence: 99%

Simulation Studies on Single-Event Effects and the Mechanisms of SiC VDMOS from a Structural Perspective

Liu,

Wang,

et al. 2023

Micromachines

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The single-event effect reliability issue is one of the most critical concerns in the context of space applications for SiC VDMOS. In this paper, the SEE characteristics and mechanisms of the proposed deep trench gate superjunction (DTSJ), conventional trench gate superjunction (CTSJ), conventional trench gate (CT), and conventional planar gate (CT) SiC VDMOS are comprehensively analyzed and simulated. Extensive simulations demonstrate the maximum SET current peaks of DTSJ−, CTSJ−, CT−, and CP SiC VDMOS, which are 188 mA, 218 mA, 242 mA, and 255 mA, with a bias voltage VDS of 300 V and LET = 120 MeV·cm2/mg, respectively. The total charges of DTSJ−, CTSJ−, CT−, and CP SiC VDMOS collected at the drain are 320 pC, 1100 pC, 885 pC, and 567 pC, respectively. A definition and calculation of the charge enhancement factor (CEF) are proposed. The CEF values of DTSJ−, CTSJ−, CT−, and CP SiC VDMOS are 43, 160, 117, and 55, respectively. Compared with CTSJ−, CT−, and CP SiC VDMOS, the total charge and CEF of the DTSJ SiC VDMOS are reduced by 70.9%, 62.4%, 43.6% and 73.1%, 63.2%, and 21.8%, respectively. The maximum SET lattice temperature of the DTSJ SiC VDMOS is less than 2823 K under the wide operating conditions of a drain bias voltage VDS ranging from 100 V to 1100 V and a LET value ranging from 1 MeV·cm2/mg to 120 MeV·cm2/mg, while the maximum SET lattice temperatures of the other three SiC VDMOS significantly exceed 3100 K. The SEGR LET thresholds of DTSJ−, CTSJ−, CT−, and CP SiC VDMOS are approximately 100 MeV·cm2/mg, 15 MeV·cm2/mg, 15 MeV·cm2/mg, and 60 MeV·cm2/mg, respectively, while the value of VDS = 1100 V.

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Study on single-event burnout of SiC VDMOSFET: failure mechanism and influence factors

Cited by 7 publications

References 13 publications

Oxide Electric Field-Induced Degradation of SiC MOSFET for Heavy-Ion Irradiation

Oxide Electric Field-Induced Degradation of SiC MOSFET for Heavy-Ion Irradiation

Study of heavy ion induced single event gate rupture effect in SiC MOSFETs

Simulation Studies on Single-Event Effects and the Mechanisms of SiC VDMOS from a Structural Perspective

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