Study the performance parameters of novel scale FINFET Device in nm Region

Jagtap, Sarika Madhukar; Gond, Vittal J.

doi:10.1109/iceca.2017.8203720

Cited by 7 publications

(6 citation statements)

References 2 publications

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“…As a result, the leakage-temperature dependency can be greatly simplified while keeping sufficient accuracy using a linear model approximation. As a result, we simulate the processor leakage power at the supply voltage/speed ( ; ) as in [20] :…”

Section: A Leakage Powermentioning

confidence: 99%

“…We express the total energy consumed by the memory in the form: (18) The characterization of memory access consists of determining e. The authors define this energy as follows: (19) With I the current consumed at each access to the memory. (20) corresponds to the current flowing in the m active cells per access, corresponds to the current necessary to store the data in the inactive cells, is the current used by the decoder, and is the circuit current peripheral. The method for evaluating these currents is not specified.…”

Section:  Memory Modelmentioning

confidence: 99%

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SoC Power Consumption Estimation at High Level of Abstraction: A Survey Study

Alali¹,

Hariti²,

Sadik³

et al. 2022

IJETAE

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Abstract—As electric energy consumption becomes a more pressing concern in System-on-a-Chip (SOC) design, accurate and efficient power analysis and estimation at all levels of abstraction throughout the design phase is becoming increasingly important in order to achieve low power without an expensive redesign process. This study examines dynamic power and leaky power analysis and estimation strategies for SOC design at several design levels that have recently been proposed, with the goal of presenting a unified view of power estimation methodologies at all design levels of abstraction, focusing especially on the high level. Keywords— System on Chip; Energy estimation; SoC modelling; Accuracy; High level of abstraction.

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Section: A Leakage Powermentioning

confidence: 99%

Section:  Memory Modelmentioning

confidence: 99%

SoC Power Consumption Estimation at High Level of Abstraction: A Survey Study

Alali¹,

Hariti²,

Sadik³

et al. 2022

IJETAE

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“…Dynamic Power Model. e charge and discharge of the capacitance C in MOSFETs are the source of dynamic power switching dissipation [14], while each low to high output transition, the load capacitance C, is charging through the PMOS transistor, and a part of energy is drawn from the power supply. A certain amount of this energy is dissipated in PMOS device and a part of it is stored on C. It is discharged during the high to low output transition, and then the stored energy is dissipated through the NMOS transistor.…”

Section: Case Studymentioning

confidence: 99%

Cosimulation of Power and Temperature Models at the SystemC/TLM for a Soft‐Core Processor

Hariti

Alali

Sadik

et al. 2020

Advances in Materials Science and Engineering

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Nowadays, modern embedded applications are becoming more and more complex and resource demanding. Fortunately, Systems on Chip (SoC) are one of the keys used to follow their requirements that stand in need of high performance while maintaining a low-power profile. On one hand, today, due to the limited power budget imposed by the batteries, power is the limiting factor of the logic CMOS. On the other hand, the downscaling of the technology node for 65 nm and beyond, based on the International Technology Roadmap for Semiconductors (ITRS) as a reference, has not only resulted in huge energy consumption but also increased the temperature chip. To address this challenge, designing at the system level is the suitable measure to tackle with the complexity of the Systems on Chip, aiming at having better adjustment between timing and accuracy for power and temperature estimations. We present in this paper, at the first stage, two models describing the static and dynamic power at the physical level. These models are implemented on an open virtual platform Model Power-Consumption and Temperature in SystemC/TLM (LIBTLMPWT) based on a representative SoC architecture. At the second stage, we focus on power, especially the thermal behaviour of the chip while running three benchmarks set on the game of life application for two different technology nodes.

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“…The increments towards the amount of the transistors precisely in a compact integrated circuit for the last four decades has been predicted by the Moore's Law due to the needs in fulfilling the demands in various operations, with the number of transistors that doubles in each two years [1,2]. Effectively, the shrinking of the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) scale has been accomplished over the years.…”

Section: Introductionmentioning

confidence: 99%

Optimization of 16 nm DG-FinFET using L25 orthogonal array of taguchi statistical method

Roslan

Salehuddin

Zain

et al. 2020

IJEECS

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The impact of the optimization using Taguchi statistical method towards the electrical properties of a 16 nm double-gate FinFET (DG-FinFET) is investigated and analyzed. The inclusion of drive current (ION), leakage current (IOFF), and threshold voltage (VTH) as part of electrical properties presented in this paper will be determined by the amendment of six process parameters that comprises the polysilicon doping dose, polysilicon doping tilt, Source/Drain doping dose, Source/Drain doping tilt, VTH doping dose, VTH doping tilt, alongside the consideration of noise factor in gate oxidation temperature and polysilicon oxidation temperature. Silvaco TCAD software is utilized in this experiment with the employment of both ATHENA and ATLAS module to perform the respective device simulation and the electrical characterization of the device. The output responses obtained from the design is then succeeded by the implementation of Taguchi statistical method to facilitate the process parameter optimization as well as its design. The effectiveness of the process parameter is opted through the factor effect percentage on Signal-to-noise ratio with considerations towards ION and IOFF. The most dominant factor procured is the polysilicon doping tilt. The ION and IOFF obtained after the optimization are 1726.88 μA/μm and 503.41 pA/μm for which has met the predictions of International Technology Roadmap for Semiconductors (ITRS) 2013.

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Study the performance parameters of novel scale FINFET Device in nm Region

Cited by 7 publications

References 2 publications

SoC Power Consumption Estimation at High Level of Abstraction: A Survey Study

SoC Power Consumption Estimation at High Level of Abstraction: A Survey Study

Cosimulation of Power and Temperature Models at the SystemC/TLM for a Soft‐Core Processor

Optimization of 16 nm DG-FinFET using L25 orthogonal array of taguchi statistical method

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