Sub-0.3V CMOS neuromorphic technology and its potential application

Abstract

The aim of this paper is to present a sub-0.3 V neuromorphic technology developed for spiking neural network design and its potential application. The main properties of the developed ultra low power (ULP) artificial neuron are first recalled. A description of ULP synapses follows that includes the plasticity scheme. The neuromorphic toolbox is then used to design a basic circuit allowing oriented edges classification. The circuit is made of 40 neurons and 108 plastic synapses, its consumed silicon core area is 0.025 mm 2 and the overall power consumption of 5 nW. Finally, the deployment of the technology within an industrial context to fabricate highly energy efficient Spike-based visual sensor is discussed.

Deep Neural Network Feasibility Using Analog Spiking Neurons

“…The ML model provides behavior close to biological neurons by using multiple complex non-linear differential equations. Such eNeuron has recently been used to implement artificial neural networks, achieving tasks such as edge recognition [9] and audio signal processing [10]. Two common concerns in such edge computing applications are circuit surface and energy consumption.…”

“…The E e f f is depicted considering the spike as a unit of information. State-of-the-art eNeurons [9], [10] are most efficient when they function at high spiking frequency, and they become increasingly E e f f -inefficient as spiking frequency lowers. ML eNeuron has a mathematical model described in the literature, being a non-linear function…”

“…In order to build an SNN, Danneville et al have proposed two new synapses in [9]. The first proposition uses inverters along with a transimpedance amplifier and a transistor biasing to generate the post-synaptic current.…”

“…Software implementations of FNNs are often used along with deep learning algorithms in order to solve highly complex problems. However, recent neuromorphic hardware is often single neuron circuits [6], [7], [8] or small neural networks [9], [10]. It is thus natural to ask if FNNs algorithms are usable on analog spiking neurons (eNeuron), to try and narrow the gap between hardware and software AI.…”

“…This paper objective is to study the deep neural network feasibility using ultra-low-power eNeuron. Previous published eNeurons from [9], [10] have been redesigned using inhouse BiCMOS 55 nm technology from ST Microelectronics. Literature synapses are revised to propose a simple, linear, and weight reconfigurable one.…”