This work presents the development for obtaining silicon nanowires (SiNW) for applications in 3D MOS devices using Focused Ion Beam with gallium ions (GaFIB) and Electron Beam Lithography (EBL) techniques. The complete fabrication process was developed for obtaining junctionless nanowire-based transistors, chosen due to the simplicity of processing and to the absence of short channel and punchthrough effects. Silicon on Insulator (SOI) wafers were used as substrate.GaFIB/SEM -a dual beam system coupled to a scanning electron microscope -, with nominal resolution for the ionic beam of 20 nm, was used to define silicon nanowires and dope them locally by gallium ions (p + -SiNW), in addition to deposit SiO 2 dielectric gate and Pt source, drain and gate electrodes. Metal electrodes and gate dielectric deposition were taken place with the electron beam available in the SEM to avoid extra ion implantation and prevent sputtering process of silicon nanowires. The dimensions obtained for the nanowire length (L Fin ) and high (H Fin ), gate length (L Gate ) and width (W Gate ) were, respectively, 6 m, 15 nm, 1 m e 35 nm. The study of the driving electric current through p + -SiNW was achieved by electrical measurements in the pseudo-MOS devices using the buried silicon dioxide (BOX) of the SOI wafer as gate dielectric to control the current through the p +
-SiNW. Electrical current between source and drain (I DS ) versus gate voltage between the back-gate and source (V BGS ) curves indicate accumulation regime for the p + -SiNW. I DS versus V DS curves indicate that the JNT device operates as a gated resistor gate.Still, the EBL techniquewith nominal resolution for the electronic beam of 2 nmwas used to fabricate nMOS JNT devices -with arsenic dopant (n + -SiNW) -along with ECR-CVC (Electron Cyclotron Resonance) chemical phase deposition plasma system, for defining the nanowires using RF plasma etching and formation of the gate dielectric. Titanium and aluminum source, drain and gate electrodes were deposited by sputtering. The dimensions of width (W) and length (L), as well as the number of nanowire transistors were varied to allow a range of up to 3 orders of the electrical current magnitude through the device. The minimum dimensions obtained for the nanowire length (L Fin ) and high (H Fin ), gate length (L Gate ) and width (W Gate ) were, respectively, 10 m, 15 nm, 100 nm e 50 nm.
xiiThe average time for the fabrication of one single JNT device using FIB system is 2 days, with the average cost of US$ 4,000.00. Still, the device fabrication using EBL technique is longerapproximately 10 days -, however it costs less than one order of magnitude compared to FIB