Sub-20 nm design technology co-optimization for standard cell logic

Abstract

Efficiency and manufacturability of standard cell logic is critical for an IC, as standard cells are at the heart of the nexus between technology definition, circuit design and physical synthesis. Conventional standard cell design techniques are increasingly ineffective as we scale to patterning restricted sub-20 nm CMOS nodes. To meet the constraints and leverage the features of future technology offerings, we propose a holistic design technology co-optimization (DTCO) for standard cell logic. In our holistic DTCO we co-optimize the standard cell architecture to balance manufacturability and efficiency at the cell level while taking into account block level considerations such as pin accessibility and power rail robustness. Our DTCO in a foundry 14 nm CMOS resulted in two standard cell architectures, namely, 10T_BiDir and 10T_UniDir. We evaluated these cell libraries with physically synthesized blocks and ring oscillator test structures in IBM 14SOI process. We observed that 10T_BiDir emerges as the preferred alternative at 14 nm CMOS, with 10T_UniDir promising better scalability to future nodes.

Design and technology co-optimization near single-digit nodes

“…Difficulty in technology porting and DTCO have been introduced for FEOL in [1] and a general overview is presented in [2] and [3]. We would like to add that FEOL complexity is increasing as local interconnect is introduced to cope with contact resistance limitations yet it significantly impacts device and circuit performance.…”

“…Discrete widths can be controlled easier in lithography but can also induce several design restrictions. 1 In technologies such as spacerbased multiple patterning, space is fixed by process due to 1 Limitations on performance optimization are studied in [8].…”

Algorithms and methodologies for interconnect reliability analysis of integrated circuits

“…However, with the technology and area shrinking, this overdesign turns unacceptable and indeed, there is a recent string of work on cell internal EM analysis [Dod15, US14]. For example, Vaidyanathan et al [VLSP14] highlights a standard cell library design methodology in which only selective routes within the standard cell are widened and how the library architecture itself is EM-aware.…”