Sub-500 ps 64 b ALUs in 0.18 μm SOI/bulk CMOS: Design & scaling trends

Abstract

The requirements of high-throughput Internet servers necessitate the use of multiple ALUs in high-performance 64b execution cores. Consequently, each ALU demands a compact, energy-efficient 64b adder core with single-cycle latency. The resultant critical path, which is a balanced mix of interconnect, diffusion and gate loads, forms a representative test bed for evaluating competing circuit techniques and process technologies (bulk CMOS/SOI). This paper presents: (i)the design of an energy-efficient 64b ALU in 0.18µm bulk CMOS technology (ii)a direct port of this design to a comparable SOI technology and (iii)an SOI-optimal redesign of the adder core. Further, it describes design margining required for the SOI implementations and reports the results of shrinking the two architectures to 0.13µm Bulk/SOI. In both cases, a sophisticated SOI compact model that incorporates features to effectively model the SOI floating body effect is used.The 64b ALU is based on a single-rail, radix-2, Han-Carlson (HC) adder core [1] with two wide multiplexer stages and a write-back bus (Figure 20.3.1). The HC adder core performs carry-merge on alternate bit slices. Consequently, it has 50% fewer carry-merge gates when compared to a conventional Kogge-Stone adder (at the cost of an additional final carry-merge stage). The reduced active leakage (21% smaller) and an efficient energy-delay characteristic make it suitable for the 64b bulk CMOS ALU (Figure 20.3.2a).

A framework for high‐speed parallel‐prefix adder performance evaluation and comparison

“…The design in , as in other microprocessor designs, has multiplexors before stage A. Some designs have multiple stages of multiplexors before and after the adder, for example, in reference .…”

“…High‐speed parallel‐prefix adders are critical building blocks in microprocessors, signal processing applications, and a variety of embedded systems . New techniques for improved speed*power efficiency as well as standby power reduction are of interest due to constraints in battery operated systems and when multiple adders may be operated in parallel.…”

“…Some adders are presented as isolated blocks where input transistor size can be quite large, leading to a faster adder, particularly if input stabilization time is not fully included in the cycle time. In practice, adders are usually a shared resource with one or more multiplexors (mux) in front to choose from several possible data sources . This places more of a restriction on the adder input transistor size and input rise/fall times, especially if the sum is fed back for immediate bypass.…”

Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

“…Increased understanding of how SOI devices behave, and possible solutions to their quirks has lead to a wider acceptance of SOI in the VLSI community. Recently, SOI has been used in a number of high-end microprocessor designs, e.g., IBM Power PC [11], [12], HP-PA 8700 [13], and others [14], [15], as well as other high-performance logic circuits [16]- [18]. The manufacturing process of SOI is very similar to that of bulk CMOS.…”

Full-custom vs. standard-cell design flow

“…In the full-custom implementation, domino gates without footers were used throughout the design except for the XOR gates where the single-ended one from [7] was used. An example of a domino gate is shown in Fig.…”